Method for Operating the Semiconductor Device

• US 20200135265A1
• Filed: 12/30/2019
• Published: 04/30/2020
• Est. Priority Date: 01/28/2016
• Status: Active Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ishizu, Takahiko, Tamura, Hikaru
• Application Number:
  US16/730,099
• Publication Number:
  US 20200135265A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations

Abstract

A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically.

Claims

1. A semiconductor device comprising:

a CPU core;

a first memory cell comprising a first capacitor, and

a second memory cell comprising a second capacitor,

wherein the CPU core is configured to write a first data read from a region where the first data is held to the first memory cell,

wherein the CPU core is configured to execute a program,

wherein the first memory cell holds a second data,

wherein the CPU core is configured to compare the first data read again from the region where the first data is held with the second data so as to determine whether the first data written to the first memory cell deteriorates and execute the program, and

wherein a refresh operation is performed on the first memory cell and the second memory cell in the case where the first data does not match the second data.

2. The semiconductor device according to claim 1,

wherein capacitance of the first capacitor is smaller than capacitance of the second capacitor.

3. The semiconductor device according to claim 1,

wherein the first memory cell comprises at least one of a first transistor and a third transistor,

wherein the second memory cell comprises at least one of a second transistor and a fourth transistor,

wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, and the fourth transistor independently comprises an oxide semiconductor comprising at least one of indium, an element M, and zinc, and

wherein the element M is aluminum, gallium, yttrium, or tin.

4. The semiconductor device according to claim 3,

wherein the first transistor is used as a write transistor, and

wherein the second transistor is used as a write transistor.

5. The semiconductor device according to claim 3,

wherein the third transistor is used as a read transistor, and

wherein the fourth transistor is used as a read transistor.

6. An electronic device comprising:

the semiconductor device according to claim 1; and

a housing.