RANDOM-ACCESS MEMORY WITH LOADED CAPACITANCE

• US 20200135266A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Raghavan, Manipatruni, Sasikanth, Chen, Gregory, Sumbul, Huseyin Ekin, Knag, Phil, Krishnamurthy, Ram, Young, Ian, Bohr, Mark, Mathuriya, Amrita
• Application Number:
  US16/175,059
• Publication Number:
  US 20200135266A1
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A loaded capacitance static random-access memory (C-SRAM) is provided. The C-SRAM is configured to prevent full bit line discharge during a functional reads even where the number of bit cells on the bit lines is small. The C-SRAM includes one or more loaded capacitance structures that may take any of a variety of physical configurations designed to provide additional capacitance to the bit lines. For instance, the loaded capacitance structures may take the form of a MIM capacitor in which a ferroelectric layer is formed from one or more high K materials. In addition, the loaded capacitance structures may be positioned in a variety of locations within the C-SRAM, including the back end of line.

Claims

1. An integrated circuit comprising:

an array of SRAM bit cells coupled to one or more bit lines; and

at least one capacitance structure coupled to the one or more bit lines and in a back end of line of the integrated circuit.

2. The integrated circuit of claim 1, wherein the at least one capacitance structure comprises a plurality of capacitance structures and each capacitance structure of the plurality of capacitance structures is coupled to a corresponding SRAM bit cell of the array of SRAM bit cells.

3. The integrated circuit of claim 1, wherein the at least one capacitance structure comprises a stack of layers.

4. The integrated circuit of claim 3, wherein the stack of layers comprises:

a first conductive layer comprising an oxide compound and a nitride compound;

a second conductive layer comprising the oxide compound and the nitride compound; and

at least one layer comprising a high-K dielectric between the first conductive layer and the second conductive layer.

5. The integrated circuit of claim 4, wherein the at least one layer comprises one or more of TiO₂, BaO, La₂O₃, HfO₂, ZrO₂, Ta₂O₅, SrO, Y₂O₃, CaO, Al₂O₃, ZrSiO₄, HfSiO₄, MgO, and Si₃N₄.

6. The integrated circuit of claim 4, wherein the at least one layer comprises oxygen and one or more of titanium, barium, lanthanum, hafnium, zirconium, tantalum, strontium, yttrium, calcium, aluminum, and magnesium.

7. The integrated circuit of claim 4, wherein the at least one layer comprises:

oxygen, silicon, and one or more of hafnium and zirconium;

or

nitrogen and silicon.

8. The integrated circuit of claim 4, wherein the at least one layer comprises a plurality of superlattice sub-layers, the plurality including first and second sub-layers each comprising a superlattice structure with high-K dielectric properties.

9. The integrated circuit of claim 8, wherein the superlattice structure for each of the first and second sub-layers comprises a bilayer structure of PbTiO₃ and SrTiO₃.

10. The integrated circuit of claim 3, wherein each layer of the stack of layers has a thickness of between 1 nm and 50 nm.

11. The integrated circuit of claim 1, wherein an amount of capacitance provided by the at least one capacitance structure is sufficient to prevent full discharge of the one or more bit lines during a functional read spanning more than 150 picoseconds.

12. The integrated circuit of claim 1, wherein an amount of capacitance provided by the at least one capacitance structure is between 10 aF and 100 fF.

13. The integrated circuit of claim 12, wherein the amount of capacitance provided by the at least one capacitance structure is between 40 fF and 70 fF.

14. The integrated circuit of claim 12, wherein the amount of capacitance provided by the at least one capacitance structure is between 30 aF and 100 aF.

15. A capacitance-loaded static random-access memory (C-SRAM) comprising the integrated circuit of claim 1.

16. A processor comprising the C-SRAM of claim 15.

17. A capacitance-loaded static random-access memory (C-SRAM) comprising:

an array of SRAM bit cells coupled to one or more bit lines; and

a plurality of capacitance structures, each capacitance structure of the plurality of capacitance structures being coupled to a corresponding SRAM bit cell of the array of SRAM bit cells.

18. The C-SRAM of claim 17, wherein each capacitance structure of the plurality of capacitance structures is disposed in a back end of line of the C-SRAM.

19. The C-SRAM of claim 17, wherein an amount of capacitance provided by each capacitance structure of the plurality of capacitance structures is between 10 aF and 100 fF.

20. The C-SRAM of claim 17, wherein an amount of capacitance provided by the plurality of capacitance structures is between 10 aF and 100 fF.

21. The C-SRAM of claim 20, wherein the amount of capacitance provided by the plurality of capacitance structures is between 30 aF and 100 aF.

22. A method of forming a capacitance-loaded static random-access memory (C-SRAM) bit cell, the method comprising:

forming an access transistor in a front end of line of the C-SRAM;

forming at least one interconnect coupled to the access transistor;

forming a metal layer coupled to the at least one interconnect, the metal layer housing at least one bit line; and

forming, in a back end of line of the C-SRAM, a capacitance structure coupled to the metal layer.

23. The method of claim 22, wherein forming the capacitance structure comprises forming a plurality of capacitance structures.

24. The method of claim 23, wherein forming the plurality of capacitance structures comprises forming each capacitance structure of the plurality of capacitance structures to comprise a plurality of layers.

25. The method of claim 24, wherein forming each capacitance structure to comprise the plurality of layers comprises forming each layer of the plurality of layers to have a thickness of between 1 nm and 50 nm.