RANDOM-ACCESS MEMORY WITH LOADED CAPACITANCE
First Claim
1. An integrated circuit comprising:
- an array of SRAM bit cells coupled to one or more bit lines; and
at least one capacitance structure coupled to the one or more bit lines and in a back end of line of the integrated circuit.
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Accused Products
Abstract
A loaded capacitance static random-access memory (C-SRAM) is provided. The C-SRAM is configured to prevent full bit line discharge during a functional reads even where the number of bit cells on the bit lines is small. The C-SRAM includes one or more loaded capacitance structures that may take any of a variety of physical configurations designed to provide additional capacitance to the bit lines. For instance, the loaded capacitance structures may take the form of a MIM capacitor in which a ferroelectric layer is formed from one or more high K materials. In addition, the loaded capacitance structures may be positioned in a variety of locations within the C-SRAM, including the back end of line.
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Citations
25 Claims
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1. An integrated circuit comprising:
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an array of SRAM bit cells coupled to one or more bit lines; and at least one capacitance structure coupled to the one or more bit lines and in a back end of line of the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A capacitance-loaded static random-access memory (C-SRAM) comprising:
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an array of SRAM bit cells coupled to one or more bit lines; and a plurality of capacitance structures, each capacitance structure of the plurality of capacitance structures being coupled to a corresponding SRAM bit cell of the array of SRAM bit cells. - View Dependent Claims (18, 19, 20, 21)
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22. A method of forming a capacitance-loaded static random-access memory (C-SRAM) bit cell, the method comprising:
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forming an access transistor in a front end of line of the C-SRAM; forming at least one interconnect coupled to the access transistor; forming a metal layer coupled to the at least one interconnect, the metal layer housing at least one bit line; and forming, in a back end of line of the C-SRAM, a capacitance structure coupled to the metal layer. - View Dependent Claims (23, 24, 25)
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Specification