BOOST SCHEMES FOR WRITE ASSIST

• US 20200135269A1
• Filed: 10/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Wei-jer, Cheng, Chiting, Lin, Yangsyu, Wu, Shang-Chi
• Granted Patent: US 11,373,702 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers

Abstract

A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

Claims

1. A write assist circuit, comprising:

a transistor switch coupled between a bit line voltage node of a cell array and a ground node;

an invertor operative to receive a boost signal responsive to a write enable signal, wherein an output of the invertor is coupled to a gate of the transistor switch; and

a metal capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate of the transistor switch, wherein the metal capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

2. The write assist circuit of claim 1, wherein the boost signal is operative to turn off the transistor switch causing discharge of the metal capacitor.

3. The write assist circuit of claim 1, wherein the metal capacitor comprises a first metal plate and a second metal plate substantially parallel to the first metal plate.

4. The write assist circuit of claim 3, wherein the first plate is in a first metal layer and the second metal plate is in a second metal layer, and wherein the first metal layer is different than the second metal layer.

5. The write assist circuit of claim 1, wherein the metal capacitor comprises hand clasping metal capacitor.

6. The write assist circuit of claim 1, wherein the metal capacitor comprises a grid style metal capacitor.

7. The write assist circuit of claim 1, wherein the metal capacitor comprises a via style metal capacitor.

8. The write assist circuit of claim 1, further comprising a metal oxide semiconductor connected in parallel to the metal capacitor.

9. The write assist circuit of claim 1, wherein the boost signal is operative to turn off the transistor switch and initiate discharging of the metal capacitor.

10. A write assist circuit comprising:

a first transistor switch connected between a word line voltage node and a supply voltage, wherein a gate of the first transistor switch is operative to receive a boost signal responsive to a write enable signal;

a second transistor switch connected between the word line voltage node and the supply voltage, wherein a gate of the second transistor switch is coupled to the word line voltage node; and

a metal capacitor having a first end coupled to the word line voltage node and a second end operative to receive the boost signal, wherein the metal capacitor is operative to drive a word line voltage of the word line voltage node to a boosted value from the supply voltage in response to the boost signal.

11. The write assist circuit of claim 10, wherein the boost signal is operative to turn off the first transistor switch, initiate charging of the metal capacitor, and boost the word line voltage.

12. The write assist circuit of claim 10, further comprising a word line driver circuit operative to provide the word line voltage to a word line of a cell array.

13. The write assist circuit of claim 10, further comprising a metal oxide semiconductor connected in parallel to the metal capacitor.

14. The write assist circuit of claim 10, wherein the metal capacitor is a hand clasping style metal capacitor comprising a first plurality of metal stripes and a second plurality of metal stripes.

15. The write assist circuit of claim 10, a length of at least one of the first plurality of metal stripes and the second plurality of metal stripes comprises a base length and an extended length, wherein the extended length is less than or equal to a word line length of a cell array.

16. The write assist circuit of claim 14, wherein the first plurality of metal stripes are in a first metal layer and the second plurality of metal stripes are formed in a second metal layer, the second metal layer being different from the first metal layer.

17. The write assist circuit of claim 14, wherein the first plurality of metal stripes form a first sub-capacitor and the second plurality of metal stripes form a second sub-capacitor, wherein the second sub-capacitor is parallel to the first sub-capacitor.

18. The write assist circuit of claim 17, wherein at least one of the first sub-capacitor and the second sub-capacitor is selectively enabled.

19. A method of negatively boosting a bit line voltage for writing data to a memory cell, the method comprising:

connecting, during a write enable period, a bit line voltage node to the ground through a first transistor switch;

turning, responsive to a boost signal, off the first transistor switch to disconnect the bit line voltage node from the ground;

initiating, after the first transistor switch is turned off, charging of a first metal capacitor having a first end coupled to the bit line voltage node and a second end coupled to a gate node of the first transistor switch, wherein charging the first metal capacitor drives the bit line voltage node to a negative voltage; and

turning, after the end of the write enabled period, on the first transistor switch to reconnect the bit line voltage node to the ground.

20. A method of claims 19 further comprising:

disconnecting, at a start of a write enable period, a word line voltage node from a supply node through a second transistor switch;

turning, responsive to a boost signal, the second transistor switch off to disconnect the word line voltage node from the supply voltage;

initiating, after the second transistor switch is turned off, charging of a second metal capacitor having a first end coupled to the word line voltage node and a second end coupled to a gate node of the second transistor switch, wherein charging of the second metal capacitor drives the word line voltage node to a boosted voltage, the boosted voltage being higher than the supply voltage; and

turning, after the end of the write enabled period, on the second transistor switch to reconnect the word line voltage node to the supply voltage.