STORAGE DEVICE AND METHOD OF OPERATING THE SAME

• US 20200135270A1
• Filed: 06/17/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Joo Young, JUNG, Hoe Seung
• Granted Patent: US 10,910,045 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

A storage device includes a memory device including a memory cell array and a page buffer group coupled to the memory cell array, and a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group, when programming of Least Significant Bit (LSB) data of a cache data chunk among the plurality of cache data chunks is completed.

Claims

1. A storage device comprising:

a memory device including a memory cell array and a page buffer group coupled to the memory cell array; and

a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and, configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group when programming Least Significant Bit (LSB) data of a current cache data chunk among the plurality of cache data chunks is completed.

2. The storage device according to claim 1, wherein the memory controller comprises:

a write buffer configured to store the plurality of cache data chunks; and

a write buffer controller configured to sequentially input the plurality of cache data chunks to the page buffer group.

3. The storage device according to claim 2, wherein the write buffer controller is configured to input the next cache data chunk to the page buffer group, when the programming of the LSB data of the current cache data chunk that is being programmed is completed.

4. The storage device according to claim 2, wherein the write buffer controller is configured to generate a data input signal for requesting input of the next cache data chunk to the page buffer group, and provide the data input signal to the write buffer, and

wherein the write buffer inputs the next cache data chunk to the page buffer group in response to the data input signal.

5. The storage device according to claim 1, wherein the memory device further comprises a cache program operation controller configured to program cache data chunks that are input to the page buffer group to the memory cell array.

6. The storage device according to claim 1, wherein the page buffer group is configured to store the next cache data chunk received from the memory controller.

7. A storage device comprising:

a memory device including a memory cell array and a page buffer group coupled to the memory cell array; and

a memory controller including a write buffer and a write buffer controller,

wherein the write buffer is configured to store a plurality of cache data chunks to be sequentially programmed, and

wherein the write buffer controller is configured to delete the previous cache data chunk from the write buffer when programming of a previous cache data chunk previously input to the page buffer group to the memory cell array has been completed while the plurality of cache data chunks are being input to the page buffer group.

8. The storage device according to claim 7, wherein the write buffer controller is configured to sequentially input the plurality of cache data chunks to the page buffer group.

9. The storage device according to claim 8, wherein the write buffer controller is configured to provide a program command for instructing each cache data chunk to be stored in the memory cell array to the memory device.

10. The storage device according to claim 8, wherein the write buffer controller is configured to delete the cache data chunk stored in the write buffer when programming of each cache data chunk to the memory cell array is completed.

11. The storage device according to claim 10, wherein the write buffer controller is configured to provide a data delete signal for requesting deletion of the cache data chunk and provide the data delete signal to the write buffer, and

wherein the write buffer is configured to delete the cache data chunk in response to the data delete signal.

12. The storage device according to claim 8, wherein the write buffer controller is configured to provide a status read command to the memory device and determine whether to delete the cache data chunk based on a status read response provided by the memory device in response to the status read command.

13. The storage device according to claim 12, wherein the status read response includes ready information indicating whether programming of the cache data chunk to the memory cell array has been completed.

14. A method for operating a storage device, the storage device comprising a memory device including a memory cell array and a page buffer group coupled to the memory cell array and a memory controller including a write buffer, the method comprising:

storing host data as a plurality of cache data chunks in the write buffer;

programming any one of the plurality of cache data chunks to the memory cell array while the plurality of cache data chunks are being sequentially input to the page buffer group; and

inputting a next cache data chunk corresponding to a next program sequence to the page buffer group when programming LSB data of a current cache data chunk has been completed.

15. The method according to claim 14, further comprising programming the next cache data chunk to the memory cell array.

16. The method according to claim 14, wherein inputting the next cache data chunk comprises:

generating a data input signal for requesting input of the next cache data chunk to the page buffer group; and

inputting the next cache data chunk to the page buffer group in response to the data input signal.

17. The method according to claim 14, further comprising deleting the current cache data chunk from the write buffer depending on whether programming of the current cache data chunk to the memory cell array has been completed.

18. The method according to claim 17, wherein the current cache data chunk is deleted from the write buffer at a time point at which the programming of the current cache data chunk to the memory cell array is completed.

19. The method according to claim 14, wherein, whether the programming of the current cache data chunk to the memory cell array has been completed is determined depending on a status read response that is provided by the memory device in response to a status read command provided by the memory controller.

20. The method according to claim 19, wherein the status read response includes ready information indicating whether the programming of the cache data chunk to the memory cell array has been completed.