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SEMICONDUCTOR MEMORY DEVICE

  • US 20200135271A1
  • Filed: 09/04/2019
  • Published: 04/30/2020
  • Est. Priority Date: 10/31/2018
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a first memory cell transistor;

    a bit line electrically connected to a first end of the first memory cell transistor;

    a source line electrically connected to a second end of the first memory cell transistor; and

    a control circuit,whereinwhen a read operation being read data from the first memory cell transistor is performed, the control circuit is configured toapply a first voltage to the bit line in a first period,apply a second voltage higher than the first voltage to the bit line and also apply a third voltage lower than the first voltage to the source line, in a second period subsequent to the first period, andsense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.

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