SEMICONDUCTOR MEMORY DEVICE

• US 20200135271A1
• Filed: 09/04/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: KAMATA, Yoshihiko, KODAMA, Takuyo, ISHIZAKI, Yuki, DEGUCHI, Yoko
• Granted Patent: US 10,861,536 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

According to one embodiment, a semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation being read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage higher than the first voltage to the bit line and also apply a third voltage lower than the first voltage to the source line, in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.

Claims

1. A semiconductor memory device comprising:

a first memory cell transistor;

a bit line electrically connected to a first end of the first memory cell transistor;

a source line electrically connected to a second end of the first memory cell transistor; and

a control circuit,

wherein

when a read operation being read data from the first memory cell transistor is performed, the control circuit is configured to

apply a first voltage to the bit line in a first period,

apply a second voltage higher than the first voltage to the bit line and also apply a third voltage lower than the first voltage to the source line, in a second period subsequent to the first period, and

sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.

2. The semiconductor memory device according to claim 1, wherein the control circuit is further configured to apply the first voltage to the source line in the first period.

3. The semiconductor memory device according to claim 2, wherein the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor, and

apply the first voltage driven by the first driver to the bit line via the first transistor.

4. The semiconductor memory device according to claim 2, wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor, and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.

5. The semiconductor memory device according to claim 1, further comprising:

a second transistor configured to electrically connect between the first end of the first memory cell transistor and the bit line;

a second memory cell transistor including a first end electrically connected to the bit line, a second end electrically connected to the source line, and a gate electrically connected to a word line electrically connected to a gate of the first memory cell transistor; and

a third transistor configured to electrically connect between the first end of the second memory cell transistor and the bit line,

wherein the control circuit is further configured to turn off the third transistor in the first period.

6. The semiconductor memory device according to claim 5, further comprising:

a fourth transistor configured to electrically connect between the second end of the second memory cell transistor and the source line,

wherein the control circuit is further configured to turn on the fourth transistor in the first period.

7. The semiconductor memory device according to claim 6, wherein the control circuit is further configured to cause the source line to be in a floating state in the first period.

8. The semiconductor memory device according to claim 7, wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor, and

apply the first voltage driven by the first driver to the bit line via the first transistor.

9. The semiconductor memory device according to claim 7, wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor, and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.

10. The semiconductor memory device according to claim 1, wherein

the first memory cell transistor is configured to store data of 2 bits or more, and

the control circuit is further configured to

sense the threshold voltage of the first memory cell transistor by use of a first read voltage in the third period,

apply the first voltage to the bit line in a fourth period subsequent to the third period,

apply the second voltage to the bit line and also apply the third voltage to the source line, in a fifth period subsequent to the fourth period, and

sense the threshold voltage of the first memory cell transistor by use of a second read voltage in a sixth period subsequent to the fifth period.

11. The semiconductor memory device according to claim 10, wherein

the control circuit is further configured to apply the first voltage to the source line in the first period and the fourth period.

12. The semiconductor memory device according to claim 11, wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor, and

apply the first voltage driven by the first driver to the bit line via the first transistor.

13. The semiconductor memory device according to claim 11, wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor, and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.

14. The semiconductor memory device according to claim 10, further comprising:

a second transistor configured to electrically connect between the first end of the first memory cell transistor and the bit line;

a second memory cell transistor including a first end electrically connected to the bit line, a second end electrically connected to the source line, and a gate electrically connected to a word line electrically connected to a gate of the first memory cell transistor; and

a third transistor configured to electrically connect between the first end of the second memory cell transistor and the bit line, and

wherein the control circuit is further configured to turn off the third transistor in the first period and the fourth period.

15. The semiconductor memory device according to claim 14, further comprising:

a fourth transistor configured to electrically connect between the second end of the second memory cell transistor and the source line, and

wherein the control circuit is further configured to turn on the fourth transistor in the first period and the fourth period.

16. The semiconductor memory device according to claim 15, wherein the control circuit is further configured to cause the source line to be in a floating state in the first period and the fourth period.

17. The semiconductor memory device according to claim 16, wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to:

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor; and

apply the first voltage driven by the first driver to the bit line via the first transistor.

18. The semiconductor memory device according to claim 16, wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to:

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor; and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.