NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20200135274A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: YI, LIANG, LI, ZHAOBING, REN, CHI
• Granted Patent: US 10,825,522 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10N 70/883 Oxides or nitrides

Abstract

A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

Claims

1. A structure of nonvolatile memory device, comprising:

a substrate, having a logic device region and a memory cell region;

a first gate structure for a low-voltage transistor, disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon; and

a second gate structure for a memory cell, disposed over the substrate in the memory cell region, wherein the second gate structure comprises;

a gate insulating layer on the substrate;

a floating gate layer on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure;

a memory dielectric layer on the floating gate layer; and

a control gate layer on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

2. The structure of nonvolatile memory device of claim 1, wherein a thickness of the control gate layer is substantially equal to a thickness of the single-layer polysilicon for the first gate structure.

3. The structure of nonvolatile memory device of claim 1, wherein the memory dielectric layer comprises an oxide/nitride/oxide (ONO) structure.

4. The structure of nonvolatile memory device of claim 1, wherein the second polysilicon layer is thicker than the first polysilicon layer.

5. The structure of nonvolatile memory device of claim 4, further comprising shallow trench isolation structures to isolate the first gate structure and the second gate structure, wherein the shallow trench isolation structures include a lower portion in the substrate.

6. The structure of nonvolatile memory device of claim 5, wherein the first polysilicon layer is lower in height than the shallow trench isolation structures.

7. The structure of nonvolatile memory device of claim 1, further comprising a third gate structure for a medium-voltage device or a high-voltage device over the substrate in the logic device region.

8. The structure of nonvolatile memory device of claim 7, wherein the third gate structure has the stacked structure of the floating gate structure.

9. The structure of nonvolatile memory device of claim 1, further comprising a gate insulating layer between the single-layer polysilicon and the substrate at the logic device region.

10. A method for fabricating nonvolatile memory device, comprising:

providing a substrate, having a logic device region and a memory cell region;

forming a first gate structure for a low-voltage transistor, disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon; and

forming a second gate structure for a memory cell, disposed over the substrate in the memory cell region, wherein the second gate structure is formed, comprising;

forming a gate insulating layer on the substrate;

forming a floating gate layer on the gate insulating layer just at the memory cell region, wherein the floating gate layer is formed by forming a first polysilicon layer and a second polysilicon layer as a stacked structure;

forming a memory dielectric layer on the floating gate layer just at the memory cell region; and

forming a control gate layer on the memory dielectric layer at a same time as forming the single-layer polysilicon in the logic device region.

11. The method for fabricating nonvolatile memory device of claim 10, wherein a thickness of the control gate layer is substantially equal to a thickness of the single-layer polysilicon for the first gate structure.

12. The method for fabricating nonvolatile memory device of claim 10, wherein the memory dielectric layer is formed by forming an oxide/nitride/oxide (ONO) layer.

13. The method for fabricating nonvolatile memory device of claim 10, wherein the second polysilicon layer is thicker than the first polysilicon layer.

14. The method for fabricating nonvolatile memory device of claim 13, further comprising forming shallow trench isolation structures with a lower portion in the substrate to isolate the first gate structure and the second gate structure.

15. The method for fabricating nonvolatile memory device of claim 14, wherein the first polysilicon layer is lower in height than the shallow trench isolation structures.

16. The method for fabricating nonvolatile memory device of claim 13, further comprising forming a third gate structure for a medium-voltage device or a high-voltage device over the substrate in the logic device region.

17. The method for fabricating nonvolatile memory device of claim 16, wherein the third gate structure has the stacked structure of the floating gate structure.

18. The method for fabricating nonvolatile memory device of claim 10, further comprising forming a gate insulating layer between the single-layer polysilicon and the substrate at the logic device region.