DYNAMIC DELAY OF NAND READ COMMANDS

• US 20200135278A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Palmer, David Aaron
• Granted Patent: US 10,685,718 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.

Claims

1. A method for increasing a probability of a parallel read within a memory die of a non-volatile memory device, the method comprising:

at a controller of the memory device, performing operations comprising;

receiving a first host read command requesting data stored on a first plane of a die of the memory device;

determining that a host read command queue does not contain a second host read command for a second plane of the die, the host read command queue queueing host read commands the host read commands requesting data stored on the die of the memory device;

responsive to determining that the host read command queue does not contain the second read command for the second plane of the die, delaying execution of the first host read command and setting a timer for a specified delay time period;

receiving, prior to expiry of the timer, a second host read command requesting data stored on a second plane of the die of the memory device; and

responsive to receiving a second host read command, causing execution of the first host read command and the second host read command in parallel.

2. The method of claim 1, wherein the delay time period is variable and is determined based upon a depth of the host read command queue.

3. The method of claim 2, comprising:

increasing the delay time period responsive to a decrease in the host read command queue.

4. The method of claim 1, wherein the method further comprises:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue does not contain a fourth host read command for a second plane of the die;

responsive to determining that the host read command queue does not contain a fourth host read command for a second plane of the die delaying execution of the third host read. command and setting a second timer for the specified delay time period;

determining that the second timer has lapsed without receipt of the fourth host read command, and in response, causing execution of the third host read command.

5. The method of claim 1, wherein causing execution of the host read command and the second host read command comprises combining the commands.

6. The method of claim 1, wherein causing execution of the host read command and the second host read command comprises canceling the timer.

7. The method of claim 1, wherein the memory device is a NAND memory device.

8. The method of claim 1, wherein the method further comprises:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue contains a fourth host read command requesting data stored on the second plane; and

responsive to determining that the host read command queue contains the fourth host read command, causing parallel execution of the third and fourth host read command without a delay period.

9. A memory device comprising:

a NAND die, the die comprising a first and second plane; and

a controller configured to perform operations comprising;

receiving a first host read command requesting data stored on a first plane of the die of the memory device;

determining that a host read command queue does not contain a second host read command for the second plane of the die. the host read command queue queueing host read commands the host read commands requesting data stored on the die of the memory device;

responsive to determining that the host read command queue does not contain the second read command for the second plane of the die, delaying execution of the first host read command and setting a timer for a specified delay time period;

receiving, prior to expiry of the timer, a second host read command requesting data stored on a second plane of the die of the memory device; and

responsive to receiving a second host read command, causing execution of the first host read command and the second host read command in parallel.

10. The memory device of claim 9, wherein the delay time period is variable and. wherein the operations comprise determining a delay time period value based upon a depth of the host read command queue.

11. The memory device of claim 10, wherein the operations further comprise:

increasing the delay time period responsive to a decrease in the host read command queue.

12. The memory device of claim 9, wherein the operations further comprise:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue does not contain a fourth host read command for a second plane of the die;

responsive to determining that the host read command queue does not contain a fourth host read command for a second plane of the die delaying execution of the third host read. command and setting a second timer for the specified delay time period;

determining that the second timer has lapsed without receipt of the fourth host read command, and in response, causing execution of the third host read command.

13. The memory device of claim 9, wherein the operations of causing execution of the host read command and the second host read command comprises combining the commands.

14. The memory device of claim 9, wherein the operations of causing execution of the host read command and the second host read command comprises canceling the timer.

15. The memory device of claim 9, wherein the operations further comprise:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue contains a fourth host read command requesting data stored on the second plane; and

responsive to determining that the host read command queue contains the fourth host read command, causing parallel execution of the third and fourth host read command without a delay period.

16. A machine-readable medium storing instructions, which when executed by a controller, cause the controller to perform operations comprising:

receiving a first host read command requesting data stored on a first plane of a die of a non-volatile memory device;

determining that a host read command queue does not contain a second host read command for a second plane of the die, the host read command queue queueing host read commands the host read commands requesting data stored on the die of the memory device;

responsive to determining that the host read command queue does not contain the second read command for the second plane of the die, delaying execution of the first host read command and setting a timer for a specified delay time period;

receiving, prior to expiry of the timer, a second host read command requesting data stored on a second plane of the die of the memory device; and

responsive to receiving a second host read command, causing execution of the first host read command and the second host read command in parallel.

17. The machine-readable medium of claim 16, wherein the delay time period is variable and wherein the operations comprise determining a delay time period value based upon a depth of the host read command queue.

18. The machine-readable medium of claim 17, wherein the operations further comprise:

increasing the delay time period responsive to a decrease in the host read command queue.

19. The machine-readable medium of claim 16, wherein the operations further comprise:

receiving a third host read command requesting data stored on the first plane of the die of the memory device;

determining that the host read command queue does not contain a fourth host read command for a second plane of the die;

responsive to determining that the host read command queue does not contain a fourth host read command for a second plane of the die, delaying execution of the third host read command and setting a second timer for the specified delay time period;

determining that the second timer has lapsed without receipt of the fourth host read command, and in response, causing execution of the third host read command.

20. The machine-readable medium of claim 16, wherein the operations of causing execution of the host read command and the second host read command comprises combining the commands.