MEMORY DEVICE AND READ OPERATION METHOD THEREOF

• US 20200135282A1
• Filed: 10/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KO, Jung-Mi, KIM, Ji-Hwan, PARK, Seong-Je
• Granted Patent: US 11,152,072 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A memory device includes a memory cell array including a plurality of memory cells, a plurality of first even page buffers suitable for reading data from first even-numbered memory cells among the plurality of memory cells, and storing the read data, a plurality of first odd page buffers suitable for reading data from first odd-numbered memory cells among the plurality of memory cells, and storing the read data, and a plurality of first cache buffers corresponding to the first even page buffers, suitable for storing data received through a first common node from the first even page buffers, and a plurality of second cache buffers corresponding to the first odd page buffers, and suitable for storing data received through the first common node from the first odd page buffers.

Claims

1. A memory device comprising:

a memory cell array including a plurality of memory cells;

a page buffer circuit suitable for reading data from even-numbered memory cells among the memory cells during a half page read operation, the page buffer circuit including a plurality of even page buffers which store the data read from the even-numbered memory cells; and

a control circuit suitable for controlling a first even page buffer and a second even page buffer of the even page buffers to simultaneously transmit the stored data through nodes which are different from each other.

2. The memory device according to claim 1, wherein the page buffer circuit further reads data from odd-numbered memory cells among the memory cells during the half page read operation, and the page buffer circuit further includes a plurality of odd page buffers which store the data read from the odd-numbered memory cells.

3. The memory device according to claim 2, wherein the control circuit controls a first odd page buffer and a second odd page buffer of the odd page buffers to simultaneously transmit the stored data through the nodes which are different from each other.

4. The memory device according to claim 3, wherein the first even and odd page buffers transmit the stored data through a first common node of the nodes which are different from each other, and the second even and odd page buffers transmit the stored data through a second common node of the nodes which are different from each other.

5. The memory device according to claim 4, wherein the page buffer circuit further includes:

first and second cache buffers suitable for storing data transmitted through the first common node from the first even and odd page buffers, respectively; and

third and fourth cache buffers suitable for storing data transmitted through the second common node from the second even and odd page buffers, respectively.

6. The memory device according to claim 1, wherein the control circuit provides a first transmission signal to control the first and second even page buffers.

7. The memory device according to claim 3, wherein the control circuit further provides a second transmission signal to control the first and second odd page buffers.

8. A memory device comprising:

a memory cell array including a plurality of memory cells;

a plurality of first even page buffers suitable for reading data from first even-numbered memory cells among the plurality of memory cells, and storing the read data;

a plurality of first odd page buffers suitable for reading data from first odd-numbered memory cells among the plurality of memory cells, and storing the read data;

a plurality of first cache buffers corresponding to the first even page buffers, and suitable for storing data received through a first common node from the first even page buffers; and

a plurality of second cache buffers corresponding to the first odd page buffers, and suitable for storing data received through the first common node from the first odd page buffers.

9. The memory device according to claim 8, further comprising:

a plurality of second even page buffers suitable for reading data from second even-numbered memory cells among the plurality of memory cells, and storing the read data;

a plurality of second odd page buffers suitable for reading data from second odd-numbered memory cells among the plurality of memory cells, and storing the read data;

a plurality of third cache buffers corresponding to the second even page buffers, and suitable for storing data received through a second common node from the second even page buffers; and

a plurality of fourth cache buffers corresponding to the second odd page buffers, and suitable for storing data received through the second common node from the second odd page buffers.

10. The memory device according to claim 9, wherein the first and second even page buffers read data from the first and second even-numbered memory cells during a half page read operation, and store the read data.

11. The memory device according to claim 10, wherein the first even page buffers sequentially transmit data read from the first even-numbered memory cells, to the first common mode, at the same time when the second even page buffers sequentially transmit data read from the second even-numbered memory cells, to the second common node.

12. The memory device according to claim 10, wherein the first and second even page buffers read data from the first and second even-numbered memory cells, and the first and second odd page buffers read data from the first and second odd-numbered memory cells.

13. The memory device according to claim 12, wherein the first odd page buffers sequentially transmit data read from the first odd-numbered memory cells, to the first common mode, at the same time when the second odd page buffers sequentially transmit data read from the second odd-numbered memory cells, to the second common node.

14. A method for operating a memory device, the method comprising:

reading data through even bit lines among a plurality of bit lines and storing the read data in even page buffers, during a half page read operation; and

transmitting data stored in first even page buffers among the even page buffers, and at the same time, transmitting data stored in second even page buffers among the even page buffers.

15. The method according to claim 14, wherein the transmitting of the data stored in the first even page buffers and the second even page buffers comprises:

sequentially activating first transmission signals corresponding to the first even page buffers, and at the same time, sequentially activating second transmission signals corresponding to the second even page buffers.

16. The method according to claim 15, wherein the transmitting of the data stored in the first even page buffers and the second even page buffers further comprises:

sequentially transmitting the data stored in the first even page buffers, to a first common node, in response to the first transmission signals; and

sequentially transmitting the data stored in the second even page buffers, to a second common node, in response to the second transmission signals.

17. The method according to claim 16, further comprising, after the storing of the read data in the even page buffers:

reading data through odd bit lines among the plurality of bit lines, and storing the read data in odd page buffers, during the half page read operation; and

transmitting data stored in first odd page buffers among the odd page buffers, and at the same time, transmitting data stored in second odd page buffers among the odd page buffers.

18. The method according to claim 17, wherein the transmitting of the data stored in the first odd page buffers and the second odd page buffers comprises:

sequentially activating third transmission signals corresponding to the first odd page buffers, and at the same time, sequentially activating fourth transmission signals corresponding to the second odd page buffers.

19. The method according to claim 18, wherein the transmitting of the data stored in the first odd page buffers and the second odd page buffers further comprises:

sequentially transmitting the data stored in the first odd page buffers, to the first common node, in response to the third transmission signals; and

sequentially transmitting the data stored in the second odd page buffers, to the second common node, in response to the fourth transmission signals.

20. The method according to claim 19, wherein the first even page buffers and the first odd page buffers transmit stored data to first cache buffers and second cache buffers, respectively, through the first common node.

21. The method according to claim 19, wherein the second even page buffers and the second odd page buffers transmit stored data to third cache buffers and fourth cache buffers, respectively, through the second common node.

22. A memory device comprising:

a memory cell array including at least first and second cell groups;

first and second buffer groups electrically coupled to the first cell group and electrically coupled to different channels; and

a control circuit configured to control the first and second buffer groups to output data of the first cell group through the corresponding channels at the same time.

23. The memory device of claim 22,

further comprising third and fourth buffer groups electrically coupled to the second cell group and electrically coupled to the respective channels,

wherein the control circuit is further configured to control the third and fourth buffer groups to output data of the second cell group through the corresponding channels at the same time.

24. An operating method of a memory device, the operating method comprising:

buffering data of a first cell group of a memory cell array including at least the first and a second cell groups into first and second buffer groups electrically coupled to different channels; and

outputting the buffered data of the first cell group through the corresponding channels at the same time.

25. The operating method of claim 24, further comprising:

buffering data of the second cell group into third and fourth buffer groups electrically coupled to the respective channels; and

outputting the buffered data of the second cell group through the corresponding channels at the same time.