MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME

• US 20200135283A1
• Filed: 05/30/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Se Chang
• Granted Patent: US 10,910,074 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory controller configured to control a memory device including a plurality of memory blocks, each including a plurality of memory cells. The memory controller may include a memory device interface configured to perform data communication with the memory device, and a soft program controller communicatively coupled to the memory device interface and configured to count a number of times that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations that the erase operation on the erase target memory block has been suspended.

Claims

1. A memory controller for controlling a memory device including a plurality of memory blocks, each including a plurality of memory cells, the memory controller comprising:

a memory device interface configured to perform data communication with the memory device; and

a soft program controller configured to count a number of iterations that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations.

2. The memory controller according to claim 1, wherein the soft program controller comprises:

a soft program setting table configured to include soft program setting information that indicates soft program operating conditions determined based on the number of iterations;

a suspend detector configured to, when the erase operation has been completed, generate suspend count information based on the number of iterations; and

a soft program processor configured to set a soft program voltage for the soft program operation based on the soft program setting information and the suspend count information.

3. The memory controller according to claim 2, wherein the soft program operating conditions comprise at least one of a soft program start bias, a soft program pulse count, and a soft program pulse bias.

4. The memory controller according to claim 2, wherein the suspend detector generates the suspend count information including a suspend count value and erase operation information, wherein the suspend count value indicates the number of iterations that the erase operation has been suspended, and the erase operation information indicates whether the erase operation has been completed.

5. The memory controller according to claim 4, wherein the suspend detector acquires the erase operation information from the memory device through a status read response indicating whether the memory device has finished an operation according to a command from the memory controller.

6. The memory controller according to claim 4, wherein the suspend detector provides the generated suspend count information to the soft program processor and initializes the suspend count information.

7. The memory controller according to claim 2, wherein the soft program processor provides, to the memory device, a soft program command for the soft program operation and a set parameter command for setting the soft program voltage.

8. The memory controller according to claim 7, wherein the soft program operation includes applying a program pulse that shifts threshold voltages of a plurality of memory cells included in the erase target memory block to a set threshold voltage distribution.

9. A method of operating a memory controller, the memory controller controlling a memory device including a plurality of memory blocks, each including a plurality of memory cells, the method comprising:

providing, to the memory device, an erase command for an erase target memory block, among the plurality of memory blocks;

providing, to the memory device, a suspend command for the erase target memory block when suspension of an erase operation on the erase target memory block is requested;

providing, to the memory device, an erase command for the erase target memory block after a suspend period corresponding to the suspend command has elapsed;

counting a number of suspend commands provided to the memory device until the erase operation is completed; and

providing a soft program command for a soft program operation on the erase target memory block based on the number of suspend commands.

10. The method according to claim 9, wherein providing the soft program command comprises generating suspend count information including a suspend count value and erase operation information,

wherein the suspend count value indicates the number of suspend commands, and

wherein the erase operation information indicates whether the erase operation has been completed.

11. The method according to claim 10, further comprising generating soft program setting information that indicates soft program operating conditions based on the generated suspend count information.

12. The method according to claim 11, wherein generating the soft program setting information comprises initializing the generated suspend count information after the soft program setting information has been generated.

13. The method according to claim 11, wherein the soft program operating conditions comprise at least one of a soft program start bias, a soft program pulse count, and a soft program pulse bias.

14. The method according to claim 11, wherein providing the soft program command further comprises providing, to the memory device, a set parameter command for setting a soft program voltage for the soft program operation based on the soft program setting information.

15. A memory controller for controlling a memory device including a plurality of memory blocks, each including a plurality of memory cells, the memory controller comprising:

a soft program setting table configured to include soft program setting information that indicates soft program operating conditions determined based on a level of a hard erase verify voltage;

a suspend detector configured to count a number of iterations that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed;

a verify voltage determinator configured to perform a hard erase verify operation on the erase target memory block based on the number of iterations, and decide on a level of a fail verify voltage that is a hard erase verify voltage used when the hard erase verify operation fails; and

a soft program processor configured to perform a soft program operation on the erase target memory block based on the level of the fail verify voltage and the soft program setting information.

16. The memory controller according to claim 15, wherein the verify voltage determinator decides on the level of the hard erase verify voltage based on the number of iterations, performs a read operation on memory cells included in the erase target memory block using the hard erase verify voltage, and decides on the level of the hard erase verify voltage as the level of the fail verify voltage when a number of OFF cells among the memory cells in the read operation, is equal to or greater than a set threshold value.

17. The memory controller according to claim 16, wherein the verify voltage determinator is further configured to, when the number of OFF cells is less than the set threshold value, perform the hard erase verify operation using an additional hard erase verify voltage lower than the hard erase verify voltage.

18. The memory controller according to claim 15, wherein the verify voltage determinator is further configured to:

perform a read operation on memory cells included in the erase target memory block using each of a plurality of hard erase verify voltages different from each other, based on the number of iterations,

determine at least one or more hard erase verify voltages for which a number of OFF cells among the memory cells in the read operation, is equal to or greater than a set threshold value, among the plurality of hard erase verify voltages, and

decide on a level of a hard erase verify voltage at which the number of OFF cells is a minimum, among the at least one or more hard erase verify voltages, as the level of the fail verify voltage.

19. The memory controller according to claim 15, wherein the soft program processor provides a soft program command for the soft program operation to the memory device, and provides, to the memory device, a set parameter command for setting a soft program voltage for the soft program operation.

20. The memory controller according to claim 15, wherein the soft program operating conditions comprise at least one of a soft program start bias, a soft program pulse count, and a soft program pulse bias.