Shift Register Unit and Driving Method, Gate Drive Circuit and Display Device
First Claim
1. A shift register unit, comprising a first input circuit, a second input circuit, an output circuit and an anti-crosstalk circuit,wherein the first input circuit is connected with a first node and configured to input a first input signal to the first node in response to a first control signal;
- the second input circuit is connected with the first node, and configured to input a second input signal to the first node in a situation where a second node is at a first level and to stop inputting the second input signal to the first node in a situation where the second node is at a second level;
the output circuit is connected with the first node, and configured to output or not output an output signal to an output terminal under control of a level of the first node; and
the anti-crosstalk circuit is connected with the second node, and is configured to prevent a level of the second node from becoming the first level in a situation where the second node is at the second level.
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Accused Products
Abstract
A shift register unit, a gate drive circuit, a display device and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit and an anti-crosstalk circuit. The first input circuit is configured to input a first input signal to a first node; the second input circuit is configured to input a second input signal to the first node in a situation where the second node is at a first level and to stop inputting the second input signal to the first node in a situation where the second node is at a second level; the output circuit is configured to output or not output an output signal; the anti-crosstalk circuit is configured to prevent a level of the second node from becoming the first level in a situation where the second node is at the second level.
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Citations
20 Claims
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1. A shift register unit, comprising a first input circuit, a second input circuit, an output circuit and an anti-crosstalk circuit,
wherein the first input circuit is connected with a first node and configured to input a first input signal to the first node in response to a first control signal; -
the second input circuit is connected with the first node, and configured to input a second input signal to the first node in a situation where a second node is at a first level and to stop inputting the second input signal to the first node in a situation where the second node is at a second level; the output circuit is connected with the first node, and configured to output or not output an output signal to an output terminal under control of a level of the first node; and the anti-crosstalk circuit is connected with the second node, and is configured to prevent a level of the second node from becoming the first level in a situation where the second node is at the second level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification