Shift Register Unit and Driving Method, Gate Drive Circuit and Display Device

• US 20200135286A1
• Filed: 08/06/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Li, Yongqian, Feng, Xuehuan
• Granted Patent: US 11,087,855 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register unit, a gate drive circuit, a display device and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit and an anti-crosstalk circuit. The first input circuit is configured to input a first input signal to a first node; the second input circuit is configured to input a second input signal to the first node in a situation where the second node is at a first level and to stop inputting the second input signal to the first node in a situation where the second node is at a second level; the output circuit is configured to output or not output an output signal; the anti-crosstalk circuit is configured to prevent a level of the second node from becoming the first level in a situation where the second node is at the second level.

Claims

1. A shift register unit, comprising a first input circuit, a second input circuit, an output circuit and an anti-crosstalk circuit,

wherein the first input circuit is connected with a first node and configured to input a first input signal to the first node in response to a first control signal;

the second input circuit is connected with the first node, and configured to input a second input signal to the first node in a situation where a second node is at a first level and to stop inputting the second input signal to the first node in a situation where the second node is at a second level;

the output circuit is connected with the first node, and configured to output or not output an output signal to an output terminal under control of a level of the first node; and

the anti-crosstalk circuit is connected with the second node, and is configured to prevent a level of the second node from becoming the first level in a situation where the second node is at the second level.

2. The shift register unit according to claim 1, wherein the anti-crosstalk circuit comprises a first transistor and a phase inverter,

the phase inverter is connected with a gate electrode of the first transistor and the second node, is between the gate electrode of the first transistor and the second node, and is configured to generate an inverted signal according to the level of the second node and to apply the inverted signal to the gate electrode of the first transistor;

and

a first electrode of the first transistor is connected with the second node, a second electrode of the first transistor is connected with a first voltage terminal to receive a first voltage, and the first transistor is configured to be turned on under control of the inverted signal generated in a situation where the second node is at the second level.

3. The shift register unit according to claim 2, wherein the phase inverter comprises a first invert transistor and a second invert transistor,

a gate electrode of the first invert transistor and a first electrode of the first invert transistor are electrically connected with each other, and are configured to be connected with a second voltage terminal to receive a second voltage, and a second electrode of the first invert transistor is connected with the gate electrode of the first transistor;

and

a gate electrode of the second invert transistor is connected with the second node, a first electrode of the second invert transistor is connected with the gate electrode of the first transistor, and a second electrode of the second invert transistor is connected with the first voltage terminal to receive the first voltage.

4. The shift register unit according to claim 2, wherein the phase inverter comprises a first invert transistor, a second invert transistor, a third invert transistor and a fourth invert transistor,

a gate electrode of the first invert transistor is connected with a first electrode of the third invert transistor, a first electrode of the first invert transistor is connected with a second voltage terminal to receive a second voltage, and a second electrode of the first invert transistor is connected with the gate electrode of the first transistor;

a gate electrode of the second invert transistor is connected with the second node, a first electrode of the second invert transistor is connected with the gate electrode of the first transistor, and a second electrode of the second invert transistor is connected with the first voltage terminal to receive the first voltage;

a gate electrode of the third invert transistor and a second electrode of the third invert transistor are electrically connected with each other, and are configured to be connected with the second voltage terminal to receive the second voltage; and

a gate electrode of the fourth invert transistor is connected with the second node, a first electrode of the fourth invert transistor is connected with a first electrode of the third invert transistor, and a second electrode of the fourth invert transistor is connected with the first voltage terminal to receive the first voltage.

5. The shift register unit o according to claim 1, wherein the anti-crosstalk circuit comprises a first transistor,

a gate electrode of the first transistor is connected with the second node, a first electrode of the first transistor is connected with the second node, and a second electrode of the first transistor is connected with a first voltage terminal to receive a first voltage, and the first transistor is configured to be turned on in a situation where the second node is at the second level.

6. The shift register unit according to claim 1, wherein the second input circuit comprises a charging sub-circuit, a storage sub-circuit and an isolation sub-circuit;

the charging sub-circuit is connected with the second node and configured to input a second control signal to the second node in response to a third clock signal;

the storage sub-circuit is connected with the second node and configured to store a level of the second control signal input by the charging sub-circuit; and

the isolation sub-circuit is connected with the second node and the first node, and configured to input the second input signal to the first node under control of the first level of the second node and a second clock signal.

7. The shift register unit according to claim 6,

wherein the charging sub-circuit comprises a second transistor, a gate electrode of the second transistor is connected with a third clock signal terminal to receive the third clock signal, a first electrode of the second transistor is connected with a blanking control terminal to receive the second control signal, and a second electrode of the second transistor is connected with the second node;

the storage sub-circuit comprises a first capacitor, a first terminal of the first capacitor is connected with the second node, and a second terminal of the first capacitor is connected with a first voltage terminal to receive a first voltage; and

the isolation sub-circuit comprises a third transistor and a fourth transistor, a gate electrode of the third transistor is connected with the second node, a first electrode of the third transistor is connected with a fourth clock signal terminal to receive a fourth clock signal, the fourth clock signal is used as the second input signal, a second electrode of the third transistor is connected with a first electrode of the fourth transistor, a gate electrode of the fourth transistor is connected with a second clock signal terminal to receive the second clock signal, and a second electrode of the fourth transistor is connected with the first node.

8. The shift register unit according to claim 1, wherein the first input circuit comprises a fifth transistor,

a gate electrode of the fifth transistor is connected with a display control terminal to receive the first control signal, a first electrode of the fifth transistor is connected with a second voltage terminal to receive a second voltage, the second voltage is used as the first input signal, and a second electrode of the fifth transistor is connected with the first node.

9. The shift register unit according to claim 1, wherein the output terminal comprises a shift output terminal and at least one scan signal output terminal.

10. The shift register unit according to claim 9, wherein the output circuit comprises a sixth transistor, a seventh transistor and a second capacitor,

a gate electrode of the sixth transistor is connected with the first node, a first electrode of the sixth transistor is connected with a first clock signal terminal to receive a first clock signal, the first clock signal is used as the output signal, and a second electrode of the sixth transistor is connected with the shift output terminal;

a gate electrode of the seventh transistor is connected with the first node, a first electrode of the seventh transistor is connected with the first clock signal terminal to receive the first clock signal, the first clock signal is used as the output signal, and a second electrode of the seventh transistor is connected with the at least one scan signal output terminal; and

a first terminal of the second capacitor is connected with the first node, and the second terminal of the second capacitor is connected with the shift output terminal.

11. The shift register unit according to claim 1, further comprising a first node noise reduction circuit, a display reset circuit, a third node control circuit and an output noise reduction circuit,

wherein the first node noise reduction circuit is configured to perform noise reduction on the first node under control of a level of a third node;

the display reset circuit is configured to reset the first node in response to a display reset signal;

the third node control circuit is configured to control the level of the third node under control of the level of the first node;

the output noise reduction circuit is configured to perform noise reduction on the output terminal under the control of the level of the third node.

12. The shift register unit according to claim 1, further comprising a blanking reset circuit,

wherein the blanking reset circuit is configured to reset the first node in response to a blanking reset signal.

13. The shift register unit according to claim 1, further comprising a first node electricity-leakage prevention circuit,

wherein the first node electricity-leakage prevention circuit is configured to control a level of a first electricity-leakage prevention node under the control of the level of the first node.

14. The shift register unit according to claim 1, further comprising a second node electricity-leakage prevention circuit,

wherein the second node electricity-leakage prevention circuit is configured to control a level of a second electricity-leakage prevention node in a situation where the second node is at the first level, to reduce electricity-leakage of the second node via the second input circuit and the anti-crosstalk circuit.

15. A gate drive circuit, comprising a plurality of cascaded shift register units, wherein each of the plurality of cascaded shift register units is the shift register unit according to claim 1.

16. The gate drive circuit according to claim 15,

wherein a display control terminal of an (n+2)th stage of shift register unit is connected with a shift output terminal of an (n)th stage of shift register unit;

and

a blanking control terminal of an (n+1)th stage of shift register unit is connected with the shift output terminal of the (n)th stage of shift register unit, and n is an integer greater than zero.

17. A display device, comprising the gate drive circuit according to claim 15.

18. A driving method of the shift register unit according to claim 1, comprising:

preventing the level of the second node from becoming the first level by the anti-crosstalk circuit in a situation where the second node is at the second level.

19. The driving method according to claim 18, further comprising:

inputting the second input signal to the first node by the second input circuit in a situation where the second node is at the first level;

stopping inputting the second input signal to the first node in a situation where the second node is at the second level; and

outputting the output signal to the output terminal under control of the level of the first node.

20. The driving method according to claim 18, further comprising:

inputting the first input signal to the first node by the first input circuit in response to the first control signal; and

outputting the output signal to the output terminal under the control of the level of the first node.