SHIFT REGISTER UNIT AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT, AND DISPLAY APPARATUS

• US 20200135287A1
• Filed: 08/30/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Han, Mingfu
• Granted Patent: US 10,902,931 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit includes: a first input sub-circuit configured to transmit a signal at a first signal input terminal to a pull-up node under control of the first signal input terminal; a second input sub-circuit configured to transmit the signal at the first signal input terminal to the pull-up node under control of a second signal input terminal; a first output sub-circuit configured to transmit a signal at a first clock signal terminal to a first signal output terminal under control of the pull-up node; and a second output sub-circuit configured to transmit a signal at a second clock signal terminal to a second signal output terminal under control of the pull-up node.

Claims

1. A shift register unit, comprising:

a first input sub-circuit connected to a first signal input terminal and a pull-up node, and configured to transmit a signal at the first signal input terminal to the pull-up node under control of the first signal input terminal;

a second input sub-circuit connected to a second signal input terminal, the first signal input terminal, and the pull-up node, and configured to transmit the signal at the first signal input terminal to the pull-up node under control of the second signal input terminal;

a first output sub-circuit connected to the pull-up node, a first clock signal terminal, and a first signal output terminal, and configured to transmit a signal at the first clock signal terminal to the first signal output terminal under control of the pull-up node; and

a second output sub-circuit connected to the pull-up node, a second clock signal terminal, and a second signal output terminal, and configured to transmit a signal at the second clock signal terminal to the second signal output terminal under control of the pull-up node.

2. The shift register unit according to claim 1, further comprising a reset sub-circuit connected to a reset signal terminal, the first signal input terminal, and the pull-up node, and configured to transmit the signal at the first signal input terminal to the pull-up node under control of the reset signal terminal.

3. The shift register unit according to claim 1, further comprising:

a first de-noising sub-circuit connected to a first pull-down node, the pull-up node, and the first signal input terminal, and configured to transmit the signal at the first signal input terminal to the pull-up node under control of the first pull-down node.

4. The shift register unit according to claim 3, further comprising:

a second de-noising sub-circuit connected to a second pull-down node, the pull-up node, and the first signal input terminal, and configured to transmit the signal at the first signal input terminal to the pull-up node under control of the second pull-down node.

5. The shift register unit according to claim 1, further comprising:

a first pull-down control sub-circuit connected to the pull-up node, a first voltage terminal, a second voltage terminal, and a first pull-down node, and configured to control a level at the first pull-down node based on levels at the first voltage terminal and the second voltage terminal under control of the pull-up node;

a first pull-down sub-circuit connected to the first pull-down node, the first signal output terminal, and a third voltage terminal, and configured to transmit a signal at the third voltage terminal to the first signal output terminal under control of the first pull-down node; and

a second pull-down sub-circuit connected to the first pull-down node, the second signal output terminal, and the second voltage terminal, and configured to transmit a signal at the second voltage terminal to the second signal output terminal under control of the first pull-down node.

6. The shift register unit according to claim 5, further comprising:

a second pull-down control sub-circuit connected to the pull-up node, a fourth voltage terminal, the second voltage terminal, and a second pull-down node, and configured to control a level at the second pull-down node based on levels at the fourth voltage terminal and the second voltage terminal under control of the pull-up node;

a third pull-down sub-circuit connected to the second pull-down node, the first signal output terminal, and the third voltage terminal, and configured to transmit the signal at the third voltage terminal to the first signal output terminal under control of the second pull-down node; and

a fourth pull-down sub-circuit connected to the second pull-down node, the second signal output terminal, and the second voltage terminal, and configured to output the signal at the second voltage terminal to the second signal output terminal under control of the second pull-down node.

7. The shift register unit according to claim 1, wherein the first input sub-circuit comprises a first transistor having a gate connected to the first signal input terminal, a first electrode connected to the first signal input terminal, and a second electrode connected to the pull-up node.

8. The shift register unit according to claim 1, wherein the second input sub-circuit comprises a second transistor having a gate connected to the second signal input terminal, a first electrode connected to the pull-up node, and a second electrode connected to the first signal input terminal.

9. The shift register unit according to claim 1, wherein the first output sub-circuit comprises a third transistor and a storage capacitor, wherein

the third transistor has a gate connected to the pull-up node, a first electrode connected to the first clock signal terminal, and a second electrode connected to the first signal output terminal;

and

the storage capacitor has a first terminal connected to the pull-up node, and a second terminal connected to the first signal output terminal.

10. The shift register unit according to claim 1, wherein the second output sub-circuit comprises a fourth transistor having a gate connected to the pull-up node, a first electrode connected to the second clock signal terminal, and a second electrode connected to the second signal output terminal.

11. The shift register unit according to claim 2, wherein the reset sub-circuit comprises a fifth transistor, wherein

the fifth transistor has a gate connected to the reset signal terminal, a first electrode connected to the pull-up node, and a second electrode connected to the first signal input terminal.

12. The shift register unit according to claim 3, wherein the first de-noising sub-circuit comprises a sixth transistor having a gate connected to the first pull-down node, a first electrode connected to the pull-up node, and a second electrode connected to the first signal input terminal.

13. The shift register unit according to claim 4, wherein the second de-noising sub-circuit comprises a seventh transistor having a gate connected to the second pull-down node, a first electrode connected to the pull-up node, and a second electrode connected to the first signal input terminal.

14. The shift register unit according to claim 5, wherein the first pull-down control sub-circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, the first pull-down sub-circuit comprises a twelfth transistor, and the second pull-down sub-circuit comprises a thirteenth transistor, wherein

the eighth transistor has a gate connected to the first voltage terminal, a first electrode connected to the first voltage terminal, and a second electrode connected to a gate of the ninth transistor and a first electrode of the tenth transistor;

the ninth transistor has the gate also connected to the first electrode of the tenth transistor, a first electrode connected to the first voltage terminal, and a second electrode connected to the first pull-down node;

the tenth transistor has a gate connected to the pull-up node, and a second electrode connected to the second voltage terminal;

the eleventh transistor has a gate connected to the pull-up node, a first electrode connected to the first pull-down node, and a second electrode connected to the second voltage terminal;

the twelfth transistor has a gate connected to the first pull-down node, a first electrode connected to the first signal output terminal, and a second electrode connected to the third voltage terminal; and

the thirteenth transistor has a gate connected to the first pull-down node, a first electrode connected to the second signal output terminal, and a second electrode connected to the second voltage terminal.

15. The shift register unit according to claim 6, wherein the second pull-down control sub-circuit comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor, the third pull-down sub-circuit comprises an eighteenth transistor, and the fourth pull-down sub-circuit comprises a nineteenth transistor, wherein

the fourteenth transistor has a gate connected to the fourth voltage terminal, a first electrode connected to the fourth voltage terminal, and a second electrode connected to a gate of the fifteenth transistor;

the fifteenth transistor has the gate also connected to a first electrode of the sixteenth transistor, a first electrode connected to the fourth voltage terminal, and a second electrode connected to the second pull-down node;

the sixteenth transistor has a gate connected to the pull-up node, and a second electrode connected to the second voltage terminal;

the seventeenth transistor has a gate connected to the pull-up node, a first electrode connected to the second pull-down node, and a second electrode connected to the second voltage terminal;

the eighteenth transistor has a gate connected to the second pull-down node, a first electrode connected to the first signal output terminal, and a second electrode connected to the third voltage terminal; and

the nineteenth transistor has a gate connected to the second pull-down node, a first electrode connected to the second signal output terminal, and a second electrode connected to the second voltage terminal.

16. A gate driving circuit, comprising N stages of cascaded shift register units according to claim 1, wherein

a first signal input terminal of an n^th stage of shift register unit is connected to a second signal output terminal of an (n−

1)^th stage of shift register unit, and a second signal input terminal of the n^th stage of shift register unit is connected to a second signal output terminal of an (n+1)^th stage of shift register unit; and

a first clock signal terminal of the n^th stage of shift register unit is connected to receive a first clock signal, and a second clock signal terminal of the n^th stage of shift register unit is connected to receive a second clock signal,

where n and N are integers greater than 1, and 2≤

n≤

N−

1.

17. A display apparatus, comprising the gate driving circuit according to claim 16.

18. A method for driving the shift register unit according to claim 1, comprising:

in an input phase, applying a first input signal at a first level to the first signal input terminal, so that the first input sub-circuit transmits the first level at the first signal input terminal to the pull-up node;

in a first output phase, applying a first clock signal at the first level to the first clock signal terminal, and applying a second clock signal at the first level to the second clock signal terminal, so that the first output sub-circuit transmits the first level at the first clock signal terminal to the first signal output terminal and the second output sub-circuit transmits the first level at the second clock signal terminal to the second signal output terminal under action of a potential at the pull-up node;

in a second output phase in which the input signal becomes a second level, the first clock signal becomes the second level, and the second clock signal is maintained at the first level, transmitting, by the first output sub-circuit, the second level at the first clock signal terminal to the first signal output terminal and transmitting, by the second output sub-circuit, the first level at the second clock signal terminal to the second signal output terminal under action of the potential at the pull-up node; and

in a pull-down phase in which the second clock signal becomes the second level, applying a second input signal at the first level to the second signal input terminal, so that the second input sub-circuit inputs the second level at the first signal input terminal to the pull-up node, and the first output sub-circuit and the second output sub-circuit are turned off under action of the potential at the pull-up node.

19. The method for driving a shift register unit according to claim 18, wherein the shift register unit comprises a reset sub-circuit, and the method for driving a shift register unit further comprises:

in a reset phase in which the first input signal at the first signal input terminal is at the second level, applying a reset signal at the first level to the reset signal terminal, so that the reset sub-circuit transmits the second level at the first signal input terminal to the pull-up node, and the first output sub-circuit and the second output sub-circuit are turned off under action of the potential at the pull-up node.

20. The method for driving a shift register unit according to claim 18, wherein

the shift register unit comprises a first de-noising sub-circuit, and the method further comprises:

in the pull-down phase, transmitting, by the first de-noising sub-circuit, the second level at the first signal input terminal to the pull-up node under control of the first pull-down node;

or

the shift register unit comprises a first de-noising sub-circuit and a second de-noising sub-circuit, and the method further comprises;

in the pull-down phase, transmitting, by the first de-noising sub-circuit, the second level at the first signal input terminal to the pull-up node under control of the first pull-down node;

or transmitting, by the second de-noising sub-circuit, the second level at the first signal input terminal to the pull-up node under control of the second pull-down node.