TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER

• US 20200135290A1
• Filed: 02/08/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: NARAYANAN, Prakash, NARESH, Nikita, INUGANTI, Prathyusha Teja, YARADUYATHINAHALLI, Rakesh Channabasappa, ACHARYA, Aravinda, SINGH, Jasbir, NARAYANAN, Naveen Ambalametil
• Granted Patent: US 10,818,374 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/822 for read only memories

Abstract

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

Claims

1. A system, comprising:

a volatile storage device;

a read-only memory (ROM);

a memory built-in self-test (BIST) controller; and

a central processing unit (CPU) to, upon occurrence of an initialization event;

execute a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device;

execute a second instruction from the ROM to change a program counter; and

execute the plurality of instructions from the volatile storage device using the program counter, the CPU, when executing the plurality of instructions, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

2. The system of claim 1, wherein:

the ROM has a first port coupled to the CPU and the ROM has a second port coupled to the memory BIST controller; and

when the CPU cause the ROM to enter the test mode, the ROM disables the first port and enables the second port.

3. The system of claim 1, wherein the CPU, when executing the plurality of instructions, also causes the ROM to exit the test mode.

4. The system of claim 3, wherein the CPU, when executing the plurality of instructions, causes the ROM to exit the test mode upon the memory BIST controller completing the test of the ROM.

5. The system of claim 3, wherein upon causing the ROM to exit the test mode, the ROM'"'"'s first port is enabled and its second port is disabled.

6. The system of claim 1, wherein the CPU, when executing the plurality of instructions, also causes the CPU to again change the program counter to a new value corresponding to an address in the ROM.

7. The system of claim 6, wherein the new value of the program counter corresponds to a ROM address following the range of addresses of the first plurality of instructions.

8. The system of claim 7, wherein the CPU executes a second instruction from the ROM to cause the CPU to determine whether the ROM passed its testing by the memory BIST controller.

9. A non-transitory storage device storing instructions, which when executed by a central processing unit (CPU), causes the CPU to:

copy a plurality of instructions from a range of addresses within the non-transitory storage device to a volatile storage device;

execute a first instruction from the non-transitory storage device to change a program counter to correspond to an address in the volatile storage device; and

execute a second instruction from the non-transitory storage device to check whether the non-transitory storage device has passed a test performed by a second device.

10. The non-transitory storage device of claim 9, wherein the second device comprises a built-in self-test controller.

11. The non-transitory storage device of claim 9, wherein the plurality of instructions to be copied to the volatile storage device comprise an instruction to cause the non-transitory storage device to disable a port to be coupled to the CPU and to cause the non-transitory storage device to enable a port to be coupled to the second device.

12. The non-transitory storage device of claim 9, wherein the plurality of instructions to be copied to the volatile storage device comprise an instruction to cause the second device to be configured to test the non-transitory storage device.

13. The non-transitory storage device of claim 9, wherein the plurality of instructions to be copied to the volatile storage device comprise an instruction to cause the CPU to wait for the second device to complete the test of the non-transitory storage device.

14. The non-transitory storage device of claim 9, wherein the plurality of instructions to be copied to the volatile storage device comprise an instruction to cause the non-transitory storage device to enable the port to be coupled to the CPU and to disable the port to be coupled to the second device.

15. The non-transitory storage device of claim 9, wherein the plurality of instructions to be copied to the volatile storage device comprise an instruction to change the program counter to correspond to an address in the ROM following the plurality of instructions.

16. A method, comprising:

copying a plurality of instructions from a range of addresses within a read-only memory (ROM) to a volatile storage device;

changing a value of a program counter to correspond to an address within the volatile storage device at the beginning of the plurality of instructions;

executing the plurality of instructions from the volatile storage device, the instructions including an instruction to change the value of the program counter to correspond to an address within the ROM following the end of the plurality of instructions within the ROM; and

executing an instruction within the ROM to determine whether the ROM passed a test.

17. The method of claim 16, further comprising performing the test of the ROM by a memory built-in self-test controller.

18. The method of claim 16, executing the plurality of instructions from the volatile storage device comprises disabling a first port of the ROM coupled to a central processing unit and enabling a second port of the ROM coupled to a memory built-in self-test controller.

19. The method of claim 18, further comprising, upon completion of the test of the ROM, enabling the first port of the ROM and disabling the second port.

20. The method of claim 16, wherein executing the plurality of instructions from the volatile storage device includes waiting on a memory built-in self-test controller to test the ROM.