SHARED ERROR CHECK AND CORRECT LOGIC FOR MULTIPLE DATA BANKS

• US 20200135291A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Takahashi, Susumu, Fujisawa, Hiroki
• Granted Patent: US 10,957,413 B2
• Time in Patent Office: Days
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1009 Data masking during input/output
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.

Claims

1. An apparatus comprising:

a first memory block of a first data bank, the first memory block comprising a first plurality of memory cells;

a second memory block of a second data bank, the second memory block comprising a second plurality of memory cells, wherein the second data bank is distinct from the first data bank; and

an error check and correct (ECC) block configured to perform ECC operations associated with memory operations that address the first memory block, or the second memory block, or both.

2. The apparatus of claim 1, wherein the ECC block comprises input circuitry and output circuitry, a first block selection circuitry configured to couple the input circuitry to the first memory block or to the second memory block based on a bank selection command, and a second block selection circuitry configured to couple the output circuitry to the first memory block or to the second memory block based on the bank selection command.

3. The apparatus of claim 2, wherein the first block selection circuitry comprises a multiplexer controlled by the bank selection command.

4. The apparatus of claim 2, wherein the second block selection circuitry comprises a first latch coupled to the first memory block and a second latch coupled to the second memory block, wherein the first latch and the second latch are controlled by the bank selection command.

5. The apparatus of claim 1, wherein the ECC block comprises:

a bit correct block configured to receive read data from the first memory block or the second memory block; and

a multiplexer comprising a first input, a second input, and a third input, wherein the first input is configured to receive the read data from the first memory block or the second memory block, the second input is configured to receive write data from a read/write bus, and the third input is configured to receive corrected data from the bit correct block.

6. The apparatus of claim 5, comprising an input/output circuit coupled to the read/write bus, wherein the input/output circuit is configured to receive data from and provide data to outside of the apparatus.

7. The apparatus of claim 5, wherein the multiplexer is configured to perform a masked-write operation by:

receiving a data mask signal;

selecting the write data from the second input when the data mask signal indicates masking; and

selecting the corrected data from the third input when the data mask signal indicates no masking.

8. The apparatus of claim 1, wherein the memory operations comprise a read operation, a write operation, or a masked-write operation.

9. The apparatus of claim 1, comprising a dynamic random access memory (DRAM) device.

10. A memory device, comprising:

control circuitry comprising a command decoder, an address decoder, and a write latency counter; and

a dynamic random access memory (DRAM) array comprising;

a plurality of data banks, wherein each data bank comprises a set of memory blocks;

a plurality of error check and correct (ECC) blocks, wherein each respective ECC block comprises a respective ECC decoder and a respective ECC syndrome decoder, and wherein each respective ECC block is configured to couple to a first memory block of a first data bank and a second memory block of a second data bank, wherein the second data bank is distinct from the first data bank; and

an ECC control logic configured to receive an initiation signal from the write latency counter and to provide triggering signals and a bank selection command to the plurality of ECC blocks.

11. The memory device of claim 10, wherein the command decoder is configured to receive a read command, a write command, and a masked-write command.

12. The memory device of claim 10, comprising an I/O circuit, a read/write bus configured to transfer data between the I/O circuit and the plurality of ECC blocks, and a data mask bus configured to provide a data mask to the plurality of ECC blocks.

13. The memory device of claim 12, wherein each respective ECC block comprises a respective 3-input multiplexer configured to receive read data from the first memory block or the second memory block via a first input, to receive write data from the read/write bus via a second input, and receive corrected data from respective bit correct blocks via a third input of the respective ECC block.

14. The memory device of claim 13, wherein each respective ECC syndrome decoder is configured to provide an error information vector to the respective bit correct blocks.

15. The memory device of claim 13, wherein each respective 3-input multiplexer is configured to perform data masking by selecting the write data via the second input when the data mask indicates no masking, and selecting the corrected data via the third input when the data mask indicates masking.

16. The memory device of claim 10, wherein the memory device comprises a double data rate (DDR) memory device, a graphics DDR (GDDR) memory device, or a low-power DDR (LPDDR) memory device.

17. A method to perform a masked-write operation using a shared error-check and correct (ECC) block coupled to a first memory block and a second memory block of a memory device, the method comprising:

retrieving first read data from the first memory block using a first bank selection circuit;

correcting the first read data using an ECC decoder, an ECC syndrome decoder, and bit correct circuitry of the ECC block to generate first corrected data;

receiving first write data from a read/write (RW) bus coupled to the ECC block;

receiving first data mask from a data mask (DM) bus coupled to the ECC block;

generating first masked-write data based on the first corrected data, the first write data and the first data mask; and

providing the first masked-write data to the first memory block using second bank selection circuit; and

wherein the memory device comprises a column-to-column (tCCD) period and the generation of the first masked-write data is performed in one tCCD period.

18. The method of claim 17, comprising:

retrieving second read data from the second memory block using the first bank selection circuit;

correcting the second read data using the ECC decoder, the ECC syndrome decoder, and the bit correct circuitry of the ECC block to generate second corrected data;

receiving second write data from the RW bus;

receiving second data mask from the DM bus;

generating second masked-write data based on the second corrected data, the second write data and the second data mask; and

providing the second masked-write data to the second memory block using the second bank selection circuit.

19. The method of claim 17, wherein generating the first masked-write data comprises selecting the first write data when the first data mask indicates no masking and selecting the first corrected data when the first data mask indicates masking.

20. The method of claim 17, wherein correcting the first read data comprises generating parity bits using the ECC decoder, determining an error information vector using the ECC syndrome decoder, and selectively inverting bits using the bit correct circuitry based on the error information vector.

21. A memory device comprising:

a first memory block belonging to a first memory bank, the first memory block comprising a first plurality of memory cells;

a second memory block belonging to a second memory bank, the second memory block comprising a second plurality of memory cells, wherein the second memory bank is distinct from the first memory bank; and

an error check and correct (ECC) block comprising an ECC circuit, wherein the first and second memory blocks share the ECC circuit.

22. The memory device of claim 21, wherein the ECC circuit comprises an input node and an output node and wherein the ECC block comprises:

a first control circuitry configured to selectively couple the input node of the ECC circuit to the first memory block or to the second memory block; and

a second control circuit configured to selectively couple the output node of the ECC circuit to the first memory block or to the second memory block.

23. The memory device of claim 21, wherein the ECC block comprises a multiplexer having a first input, a second input, and a third input, wherein the first input is configured to receive an output from either the first memory block or the second memory block and the second input is configured to receive a data signal from a read/write (RW) bus, and wherein the ECC circuit comprises an error corrector configured to receive the output from either the first memory block or the second memory block and provide its output to the third input of the multiplexer.

24. The memory device of claim 23, comprising a data input/output circuit coupled to the RW bus, the data input/output circuit configured to receive and provide data from and to outside of the memory device.