MEMORY MODULES AND METHODS OF OPERATING MEMORY SYSTEMS INCLUDING THE SAME

• US 20200135292A1
• Filed: 04/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Hyun-Joong, KIM, Duk-Sung, LEE, Yoo-Jung, CHOI, Jang-Seok
• Granted Patent: US 10,867,690 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1024 Identification of the type of error
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/783 with refresh of replacement cells, e.g. in DRAMs
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

Claims

1. A memory module comprising:

a plurality of first data memories and a first error correction code (ECC) memory that constitute a first channel; and

a plurality of second data memories and a second ECC memory that constitute a second channel,

wherein each of the plurality of first data memories is configured to transmit a corresponding first data set of a plurality of first data sets with a memory controller, each of the plurality of first data sets corresponding to a burst length,

each of the plurality of second data memories is configured to transmit a corresponding second data set of a plurality of second data sets with the memory controller, each of the plurality of second data sets corresponding to the burst length,

the first ECC memory is configured to store first sub parity data for detecting at least one error in all of the plurality of first data sets stored in the plurality of first data memories, and

the second ECC memory is configured to store second sub parity data for detecting at least one error in all of the plurality of second data sets stored in the plurality of second data memories.

2. The memory module of claim 1, wherein:

each of the plurality of first data memories has a 4-bit data input/output (I/O) width;

each of the plurality of second data memories has a 4-bit data IO width; and

each of the first ECC memory and the second ECC memory stores has a 4-bit data I/O width.

3. The memory module of claim 2,

wherein each of the first channel and the second channel has a 36-bit data input/output width.

4. The memory module of claim 1, wherein:

each of the plurality of first data memories includes a memory cell array that having a first memory region and a second memory region;

the first memory region of each of the plurality of first data memories stores a corresponding first data set of the plurality of first data sets and the second memory region stores first parity bits generated from an ECC encoding operation performed on the corresponding first data set; and

the first parity bits are part of the first sub parity data.

5. The memory module of claim 4,

wherein each of the plurality of first data memories includes an ECC engine including:

an ECC encoder configured to perform the ECC encoding operation on the corresponding first data set of the plurality of first data sets to generate the first parity bits; and

an ECC decoder configured to perform an ECC decoding operation on a corresponding first data set of the plurality of first data sets read from the first memory region to correct an error detected from the corresponding first data set of the plurality of first data sets which are read from the first memory region.

6. The memory module of claim 1, wherein:

the first ECC memory includes a first parity region and a second parity region;

the first parity region stores the first sub parity data; and

the second parity region stores internal parity bits generated based on the first sub parity data.

7. The memory module of claim 6,

wherein the first ECC memory further includes an ECC engine including:

an ECC encoder configured to perform an ECC encoding operation on the first sub parity data to generate the internal parity bits; and

an ECC decoder configured to perform an ECC decoding operation on the first sub parity data read from the first parity region to correct an error detected in the first sub parity data.

8. The memory module of claim 1, wherein:

the second ECC memory includes a first parity region and a second parity region;

the first parity region stores the second sub parity data; and

the second parity region stores internal parity bits generated based on the second sub parity data.

9. The memory module of claim 8,

wherein the second ECC memory further includes an ECC engine including:

an ECC encoder configured to perform an ECC encoding operation on the second sub parity data to generate the internal parity bits; and

an ECC decoder configured to perform an ECC decoding operation on the second sub parity data read from the first parity region to correct an error detected in the first sub parity data.

10. The memory module of claim 1, wherein:

a first error of at least one first data memory of the plurality of first data memories is detected and corrected based on the first sub parity data stored in the first ECC memory; and

a second error of at least one second data memory of the plurality of second data memories is detected and corrected based on the second sub parity data stored in the second ECC memory.

11. A memory module comprising:

a first channel including a plurality of first data memories;

a second channel including a plurality of second data memories; and

an error correction code (ECC) memory,

wherein the plurality of first data memories and the plurality of second data memories store a plurality of first data sets and a plurality of second data sets respectively,

each of the plurality of first data sets corresponds to a burst length,

each of the plurality of second data sets corresponds to the burst length, and

the ECC memory is configured to store parity data for detecting at least one error in at least one of a first sub user data set corresponding to all of the plurality of first data sets and a second sub user data set corresponding to all of the plurality of second data sets.

12. The memory module of claim 11, wherein:

each of the plurality of first data memories has an 8-bit data input/output (I/O) width,

each of the plurality of second data memories has an 8-bit data I/O width; and

the ECC memory has an 8-bit data IO width.

13. The memory module of claim 11, wherein:

the ECC memory includes a first parity region and a second parity region;

the first parity region stores at least one of first sub parity data associated with the first sub user data set and second sub parity data associated with the second sub user data set; and

the second parity region stores at least one of the first sub parity data and the second sub parity data.

14. The memory module of claim 13, further comprising a buffer device,

wherein the buffer device is configured to redistribute a command and an address received from an external memory controller to each of the plurality of first data memories, each of the plurality of second data memories and the ECC memory, and

the buffer device is configured to apply a pseudo channel selection signal to the ECC memory to activate at least one of the first parity region and the second parity region.

15. The memory module of claim 14, wherein:

the first parity region, if activated by the pseudo channel selection signal, stores the first sub parity data during operation of the first channel;

the second parity region, if activated by the pseudo channel selection signal, stores the second sub parity data during operation of the second channel;

the first channel further includes the first parity region; and

the second channel further includes the second parity region.

16. The memory module of claim 14, wherein:

the first parity region and the second parity region, if activated by the pseudo channel selection signal, store the first sub parity data during operation of the first channel;

the first parity region and the second parity region, if activated by the pseudo channel selection signal, store the second sub parity data during operation of the second channel;

each of the first channel and the second channel further includes the first parity region and the second parity region; and

the first parity region and the second parity region are shared by the first channel and the second channel.

17. The memory module of claim 14, wherein:

the first parity region and the second parity region are enabled by the pseudo channel selection signal to store the first sub parity data during operation of the first channel;

the first parity region and the second parity region are disabled during operation of the second channel; and

the first channel further includes the first parity region and the second parity region.

18. The memory module of claim 11,

wherein each of the plurality of first data memories further include an ECC engine including:

an ECC encoder configured to perform an ECC encoding operation on a corresponding first data set of the plurality of first data sets to generate first parity bits; and

an ECC decoder configured to perform an ECC decoding operation on a corresponding first data set of the plurality of first data sets read from the ECC memory to correct an error detected from the corresponding first data set of the plurality of first data sets which are read from the ECC memory.

19. The memory module of claim 11,

wherein the ECC memory is configured to correct an error bit of at least one first data memory of the plurality of first data memories based on the parity data and the error bit is detected in the plurality of first data sets.

20. A method of operating a memory system, wherein the memory system includes a memory module and a memory controller to control the memory module and the memory module includes a plurality of first data memories, a plurality of second data memories and an error correction code (ECC) memory, the method comprising:

storing each of a plurality of first data sets corresponding to a burst length in a corresponding first data memory of the plurality of first data memories;

storing each of a plurality of second data sets corresponding to the burst length in a corresponding second data memory of the plurality of second data memories;

storing, in the ECC memory, first sub parity data associated with all of the plurality of first data sets and second sub parity data associated with all of the plurality of second data sets;

detecting, by the memory controller, whether each of the plurality of first data memories and the plurality of second data memories has an error bit based on all of the plurality of first data sets and all of the plurality of second data sets;

determining, by the memory controller, whether the detected error bit is correctable based on the first sub parity data and the second sub parity data; and

flipping, by the memory controller, a data value of the detected error bit in response to determining that the detected error bit is not correctable.