SELECTIVE DEPOSITION BY LASER HEATING

• US 20200135465A1
• Filed: 01/15/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: OUYANG, Christine Y
• Granted Patent: US 11,087,984 B2
• Time in Patent Office: Days
• CPC Class Codes: C23C 16/0209 by heating
• CPC Class Codes: C23C 16/04 Coating on selected surface areas, e.g. using masks
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/45527 characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
• CPC Class Codes: C23C 16/46 characterised by the method used for heating the substrate C23C16/48, C23C16/50 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a first material and a second material on a semiconductor substrate. The first material is different from the second material. The method also includes heating the first material to a first temperature and the second material to a second temperature with a laser beam. The first temperature is different from the second temperature. The method also includes depositing a third material on the first material.

Claims

1. A method for forming a semiconductor structure, comprising:

forming a first material and a second material on a semiconductor substrate, wherein the first material is different from the second material;

heating the first material to a first temperature and the second material to a second temperature with a laser beam, wherein the first temperature is higher than the second temperature; and

depositing a first precursor on the first material;

depositing a second precursor on the first material; and

reacting the first precursor and the second precursor to form a third material on the first material.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the first temperature is in a range from about 200°

C. to about 600°

C.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein the first precursor is deposited on the first material in a chamber, and the second precursor is deposited on the first material in the chamber.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein the laser beam heats the first material to the first temperature and the second material to the second temperature during the deposition of the first precursor.

5. The method for forming a semiconductor structure as claimed in claim 1, wherein the first temperature is higher than the second temperature by about 100°

C. to about 300°

C.

6. The method for forming a semiconductor structure as claimed in claim 1, further comprising:

forming a fin structure over the semiconductor substrate;

forming a source/drain structure on the fin structure, wherein the first material is formed on the source/drain structure;

forming a gate structure across and on the fin structure; and

planarizing the third material on the first material, wherein a top surface of the third material and a top surface of the second material are coplanar.

7. A method for forming a semiconductor structure, comprising:

forming a first material and a second material on a semiconductor substrate, wherein the first material is different from the second material;

coating a heat-curable layer on the first material and the second material;

heating the first material and the second material with a laser beam, wherein the laser beam heats the first material to a first temperature, and the laser beam heats the second material to a second temperature that is higher than the first temperature;

removing a first portion of the heat-curable layer on the first material to expose the first material while leaving a second portion of the heat-curable layer on the second material;

depositing a third material on the first material; and

removing the second portion of the heat-curable layer.

8. The method for forming a semiconductor structure as claimed in claim 7, wherein a ratio of a first thickness of a first portion of the third material on the second material to a second thickness of a second portion of the third material on the first material is in a range from about 0.001 to about 0.1.

9. The method for forming a semiconductor structure as claimed in claim 8 wherein a ratio of the first thickness of the first portion of the third material on the second material to a third thickness of the second portion of the heat-curable layer is in a range from about 0.001 to about 0.1.

10. The method for forming a semiconductor structure as claimed in claim 7, wherein a first hardness of the first portion of the heat-curable layer on the first material is lower than a second hardness of the second portion of the heat-curable layer on the second material during or after heating the first material and the second material with the laser beam.

11. The method for forming a semiconductor structure as claimed in claim 7, wherein the second temperature is higher than the first temperature by about 100°

C. to about 300°

C.

12. The method for forming a semiconductor structure as claimed in claim 7, further comprising:

forming a fin structure on the semiconductor substrate, wherein the first material is formed across the fin structure and is configured to be a gate electrode layer; and

planarizing the third material on the gate electrode layer, wherein a top surface of the third material and a top surface of the second material are coplanar.

13. A method for forming a semiconductor structure, comprising:

forming a first material and a second material on a semiconductor substrate, wherein the first material is different from the second material;

heating the first material to a first temperature and the second material to a second temperature with a laser beam, wherein a difference between the first temperature and the second temperature is in a range from about 100°

C. to about 300 t; and

selectively depositing a third material on the first material.

14. The method for forming a semiconductor structure as claimed in claim 13, wherein the first material is a metal, and the second material is a dielectric material.

15. The method for forming a semiconductor structure as claimed in claim 14, further comprising:

forming a fin structure over the semiconductor substrate, wherein the first material is formed across the fin structure and is configured to be a gate electrode layer.

16. The method for forming a semiconductor structure as claimed in claim 15, further comprising:

planarizing the third material on the gate electrode layer, wherein a top surface of the gate electrode layer is lower than a top surface of the second material, and a top surface of the third material is level with the top surface of the second material.

17. The method for forming a semiconductor structure as claimed in claim 14, further comprising:

forming a fin structure on the semiconductor substrate;

forming a source/drain structure on the fin structure; and

forming a gate structure across and on the fin structure, wherein the first material is formed over the source/drain structure.

18. The method for forming a semiconductor structure as claimed in claim 17, further comprising:

planarizing the third material on the first material, wherein a top surface of the first material is lower than a top surface of the second material, and a top surface of the third material is level with the top surface of the second material.

19. The method for forming a semiconductor structure as claimed in claim 13, wherein a wavelength of the laser beam is in a range from about 600 nm to about 1000 nm.

20. The method for forming a semiconductor structure as claimed in claim 13, wherein the laser beam heats the first material and the second material for about 0.01 milliseconds to about 10 milliseconds.