Semiconductor Device and Method of Forming

• US 20200135474A1
• Filed: 07/02/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shu-Han, Chen, Tsung-Ju, Kung, Ta-Hsiang, Yu, Xiong-Fei, Chui, Chi On
• Granted Patent: US 11,069,531 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/28141 insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Claims

1. A method, comprising:

forming a dummy dielectric layer over a substrate;

forming a dummy gate over the dummy dielectric layer;

forming a first spacer adjacent the dummy gate;

removing the dummy gate to form a cavity, wherein the cavity is defined at least in part by the first spacer;

performing a plasma treatment on portions of the first spacer, wherein the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition;

etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition; and

filling the cavity with a plurality of conductive materials to form a gate structure.

2. The method according to claim 1, wherein the gate structure extends along remaining portions of the first spacer.

3. The method according to claim 1, further comprising etching the dummy dielectric layer, wherein the portions of the first spacer having the second material composition and the dummy dielectric layer are etched in a single etching process.

4. The method according to claim 1, wherein a depth of penetration of the plasma treatment into the first spacer varies according to a height of the first spacer.

5. The method according to claim 1, wherein etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition causes remaining portions of the first spacer to have tapered sidewalls, wherein the tapered sidewalls face the cavity.

6. The method according to claim 5, wherein a first tapered sidewall of the tapered sidewalls forms an angle with respect to a direction that is perpendicular to a major surface of the substrate, and the angle is in a range from 3 degrees to 50 degrees.

7. The method according to claim 1, wherein etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition causes a top opening of the cavity to widen.

8. The method according to claim 7, wherein the cavity is filled with the plurality of conductive materials through the top opening.

9. The method according to claim 1, wherein the first material composition comprises oxygen at a first concentration, the second material composition comprises oxygen at a second concentration, and wherein the second concentration is greater than the first concentration.

10. The method according to claim 9, wherein the first material composition comprises nitrogen at a third concentration and carbon at a fourth concentration, and the second material composition comprises nitrogen at a fifth concentration and carbon at a sixth concentration, and wherein the fifth concentration is less than the third concentration and the sixth concentration is less than the fourth concentration.

11. A method, comprising:

depositing and patterning a dummy gate over a dummy dielectric layer;

forming a plurality of spacers surrounding the dummy gate;

etching the dummy gate to form a gate cavity, the gate cavity being defined by the plurality of spacers;

performing a plasma treatment on at least a portion of a first spacer of the plurality of spacers, wherein the portion of the first spacer is at least a portion of the first spacer that is farthest from the dummy dielectric layer;

performing an etch process to remove the portion of the first spacer and a portion of the dummy dielectric layer, wherein after the etch process is completed a top opening of the gate cavity has been widened;

depositing one or more gate dielectric layers and one or more gate electrode layers in the gate cavity through the top opening to form a gate structure; and

forming an interlayer dielectric (ILD) surrounding the plurality of spacers.

12. The method according to claim 11, further comprising performing a planarization process to planarize the ILD and the gate structure.

13. The method according to claim 12, wherein after the planarization process has been performed, a sidewall of the one or more gate dielectric layers extends at an angle with respect to a direction that is perpendicular to a planarized surface of the ILD, and wherein the angle is in a range of 3 degrees to 50 degrees.

14. The method according to claim 11, wherein performing the etch process to remove the portion of the first spacer causes remaining portions of the first spacer to have tapered sidewalls.

15. The method according to claim 11, wherein the one or more gate dielectric layers and the one or more gate electrode layers comprise tapered sidewalls along portions of the one or more gate electrode layers and the one or more gate dielectric layers that extend along a remaining portion of the first spacer.

16. The method according to claim 11, wherein the plasma treatment changes a material composition of the portion of the first spacer from a first material composition to a second material composition.

17. A device, comprising:

a plurality of source/drain regions formed in a substrate;

a gate structure over the substrate between the plurality of source/drain regions, wherein the gate structure comprises one or more gate dielectric layers and one or more gate electrode layers; and

a plurality of spacers surrounding the gate structure, wherein a first spacer of the plurality of spacers contacts the one or more gate dielectric layers, wherein the first spacer has a first thickness at a first location and a second thickness at a second location, wherein the first location is farthest from the substrate and the second location is between the first location and the substrate, and wherein a first sidewall of the first spacer that contacts the one or more gate dielectric layers extends at an angle between the first location and the second location, the angle is with respect to a direction that is perpendicular to a major surface of the substrate, and the angle is greater than or equal to 3 degrees.

18. The device according to claim 17, wherein a sidewall of the one or more gate dielectric layers that contacts the first spacer extends at the same angle as the first sidewall of the first spacer.

19. The device according to claim 17, wherein a second sidewall of the first spacer extends in the direction that is perpendicular to the major surface of the substrate, the second sidewall being opposite to the first sidewall.

20. The device according to claim 17, wherein a thickness of the first spacer varies according to height of the first spacer between the first location and the second location, wherein the height is in the direction that is perpendicular to the major surface of the substrate.