BORON-DOPED AMORPHOUS CARBON HARD MASK AND RELATED METHODS

• US 20200135485A1
• Filed: 10/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Entegris Incorporated
• Original Assignee: Entegris Incorporated
• Inventors: UVAIS, Ajith, BISHOP, Steve E.
• Granted Patent: US 11,049,728 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02351 treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/469 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After-treatment of these layers

Abstract

Described are boron-doped amorphous carbon hard masks, methods of preparing boron-doped amorphous carbon hard masks, methods of using the boron-doped amorphous carbon hard masks, and devices that include the boron-doped amorphous carbon hard masks.

Claims

1. A method of preparing a microelectronic device substrate, the method comprising:

implanting boron by ion implantation into an amorphous carbon layer of a substrate that comprises one or more layers of a microelectronic device and the amorphous carbon hardmask layer at a top surface, and

annealing the amorphous carbon hardmask layer.

2. The method of claim 1 wherein the boron-doped amorphous carbon hardmask layer, after annealing, has an increased etch resistance compared to an etch resistance of a comparable boron-doped amorphous carbon hardmask layer that has not been annealed.

3. The method of claim 1 comprising implanting the boron at a relatively higher concentration at an upper portion of a thickness of the amorphous carbon hardmask layer and at a relatively lower concentration at a lower portion of the thickness.

4. The method of claim 1 comprising annealing the amorphous carbon hardmask layer during ion implantation of the boron.

5. The method of claim 1 comprising heating the substrate to a temperature in a range from 150 to 400 degrees Celsius during annealing.

6. The method of any of claims 1 wherein the amorphous carbon hardmask layer has a thickness in a range from 0.5 to 5 microns.

7. A method of any of claim 1 comprising etching the amorphous carbon hardmask layer to form openings in the amorphous carbon hardmask layer before implanting the boron by ion implantation.

8. A method of claim 7 comprising etching the substrate through the openings in the hardmask layer to form an opening in the substrate, the opening in the substrate having an aspect ratio of at least 40:

1.

9. A method of claim 8 wherein the opening in the substrate is a channel hole.

10. The method of claim 1, comprising forming a patterned mask on the carbon amorphous layer;

and etching the amorphous carbon hardmask layer to form openings in the amorphous carbon hardmask layer before implanting the boron by ion implantation

11. The method of claim 8 wherein the substrate etching step includes exposing material of the substrate to a fluorinated or perfluorinated gaseous etchant.

12. The method of claim 11 comprising, after etching the substrate, removing a remaining portion of the hardmask layer by oxygen plasma etching.

13. The method of claim 1 wherein the substrate comprises a filmstack comprising multiple layers of silicon-containing materials.

14. The method of claim 1 wherein the substrate comprises multiple layers of silicon oxide and silicon nitride.

15. A microelectronic device substrate comprising:

one or more layers of a microelectronic device;

on an upper surface of the one or more layers, a boron-doped hardmask layer comprising a first surface contacting the upper surface of the microelectronic device, an exposed surface, a thickness between the first surface and the exposed surface, and openings extending through the thickness;

the boron-doped hardmask layer comprising amorphous carbon and implanted boron, with the boron being present at a relatively higher concentration at an upper portion of a thickness of the amorphous carbon hardmask layer and at a relatively lower concentration at a lower portion of the thickness, and the boron-doped hardmask layer being annealed.

16. The substrate of claim 15 wherein the annealed boron-doped amorphous carbon hardmask layer has an etch resistance that is increased relative to an etch resistance of a comparable boron-doped amorphous carbon hardmask layer that is not annealed.

17. The substrate of claim 15 wherein the amorphous carbon hardmask layer has a thickness in a range from 0.5 to 10 microns.