PATTERN FORMATION METHOD AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

• US 20200135487A1
• Filed: 05/31/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Yi-Chang, LIN, Jiann-Horng, CHEN, Chih-Hao, WU, Ying-Hao, CHEN, Wen-Yen, TSENG, Shih-Hua, SUEN, Shu-Huei
• Granted Patent: US 10,943,791 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks

Abstract

In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.

Claims

1. A pattern formation method, comprising:

forming a photo resist pattern over a target layer to be patterned;

forming an extension material layer on the photo resist pattern; and

patterning the target layer by using at least the extension material layer as an etching mask.

2. The pattern formation method of claim 1, wherein:

the photo resist pattern includes line patterns, and

the extension material layer is formed on each of the line patterns.

3. The pattern formation method of claim 2, wherein:

the extension material layer is formed on a surface of the target layer between the line patterns, and

a thickness T1 of the extension material layer formed on the surface of the target layer between the line patterns and a thickness T2 of the extension material layer formed on each of the line patterns satisfy 2≤

T2/T1.

4. The pattern formation method of claim 3, wherein 30≤

T2/T1≤

300.

5. The pattern formation method of claim 3, further comprising etching the extension material layer formed on a surface of the target layer before the target layer is etched.

6. The pattern formation method of claim 2, wherein an aspect ratio of each of the line patterns is at least 2.

7. The pattern formation method of claim 6, wherein a space between adjacent line patterns is in a range from about 5 nm to about 20 nm.

8. The pattern formation method of claim 1, wherein the extension material layer is formed by chemical vapor deposition (CVD) under a non-conformal deposition condition.

9. The pattern formation method of claim 8, wherein the CVD is plasma CVD performed under a pressure equal to or higher than 20 mTorr.

10. The pattern formation method of claim 8, wherein the extension material layer includes one selected from the group consisting of a carbon based material, a silicon oxide based material, and a silicon nitride based material.

11. The pattern formation method of claim 8, wherein a source gas for the CVD includes one selected from the group consisting of hydro carbon and fluorocarbon.

12. The pattern formation method of claim 8, wherein a source gas for the CVD includes a silicon containing gas.

13. A method of manufacturing a semiconductor device, comprising:

forming a photo resist pattern over a target layer to be patterned;

performing a descum etching to remove photo resist residue;

forming an extension material layer on the photo resist pattern; and

patterning the target layer by using at least the extension material layer as an etching mask.

14. The method of claim 13, wherein the descum etching is performed after the extension material layer is formed.

15. The method of claim 13, wherein in the descum etching, a part of the target layer is etched.

16. The method of claim 13, wherein:

the descum etching includes a first descum etching and a second descum etching performed under a different condition than the first descum etching, and

the extension material layer is formed between the first descum etching and the second descum etching.

17. The method of claim 16, wherein:

the first descum etching is performed before the extension material layer is formed and an etching gas includes fluorine, and

the second descum etching is performed after the extension material layer is formed and an etching gas includes chlorine.

18. A method of manufacturing a semiconductor device, comprising:

forming a first dielectric layer over a semiconductor substrate;

forming a nitrogen-free layer over the first dielectric layer;

forming a metallic hard mask layer over the nitrogen-free layer;

forming a second dielectric layer over the metallic hard mask layer;

forming a third dielectric layer over the second dielectric layer;

forming a fourth dielectric layer over the third dielectric layer;

forming a photo resist pattern over a fourth dielectric layer layer;

performing a descum etching to remove photo resist residue;

forming an extension material layer on the photo resist pattern; and

patterning the fourth dielectric layer by using at least the extension material layer as an etching mask.

19. The method of claim 18, further comprising:

patterning the third dielectric layer by using the patterned fourth dielectric layer as an etching mask;

patterning the second dielectric layer and the metallic hard mask layer by using the patterned third dielectric layer as an etching mask; and

patterning the first dielectric layer by using the patterned metallic hard mask layer and second dielectric layer as an etching mask.

20. The method of claim 19, wherein:

the first dielectric layer is made of a low-k dielectric material, and

the metallic hard mask layer is made of TiN.