METHOD OF FABRICATING INTEGRATED CIRCUITS

• US 20200135490A1
• Filed: 10/14/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: SPTS Technologies Limited (KLA Corporation)
• Original Assignee: SPTS Technologies Limited (KLA Corporation)
• Inventors: WILBY, TONY, BURGESS, STEVE
• Granted Patent: US 11,361,975 B2
• Time in Patent Office: Days
• CPC Class Codes: H01J 37/32871 Means for trapping or directing unwanted particles
• CPC Class Codes: H01J 37/32926 Software, data control or modelling
• CPC Class Codes: H01J 37/32972 Spectral analysis
• CPC Class Codes: H01L 21/32131 by physical means only
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03614 by chemical means only
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A method of fabricating an integrated circuit is disclosed. The method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process comprises the steps of: plasma etching an excess metal portion of the metal interconnection layer using plasma comprising a noble gas, for an etch duration. The method further comprises stopping the etch process prior to the excess metal portion being completely removed and thus prior to a dielectric surface upon which the metal interconnection is formed, becoming completely exposed. The remaining excess metal portion comprising excess metal residues is subsequently removed using a second etch step.

Claims

1. A method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process, the metal interconnection layer being disposed between a dielectric layer and an integrated circuit, the method comprising the steps of:

plasma etching an excess metal portion of the metal interconnection layer for an etch duration, using a plasma comprising a noble gas, the excess metal portion being disposed on a surface of the dielectric layer;

controlling the etch duration so as to stop the plasma etching before the excess metal portion is completely removed from the dielectric layer;

etching the remaining excess metal portion to remove excess metal residues from the dielectric layer.

2. A method according to claim 1, wherein the noble gas comprises argon.

3. A method according to claim 1, wherein the etching of the remaining excess metal portion comprises wet chemical etching.

4. A method according to claim 1, wherein the etching of the remaining excess metal portion comprises chemical dry etching.

5. A method according to claim 4, wherein the chemical dry etching comprises etching using a fluorocarbon.

6. A method according to claim 5, wherein the fluorocarbon comprises tetrafluoromethane.

7. A method according to claim 5, wherein the chemical dry etching comprises etching using chlorine.

8. A method according to claim 1, wherein the excess metal portion comprises a barrier layer or layers disposed on the dielectric layer and a copper layer disposed on the barrier layer(s).

9. A method according to claim 8, wherein the excess metal residues comprise barrier layer residues.

10. A method according to claim 1, further comprising dynamically calculating the etch duration during the etch process.

11. A method according to claim 10, wherein the etch duration is set when the surface of the dielectric layer is detected during the plasma etching.

12. A method according to claim 10, wherein the surface of the dielectric layer is detected using optical emission spectroscopy (OES) or secondary ion mass spectroscopy (SIMS).

13. A method according to claim 1, further comprising calculating the etch duration prior to plasma etching, wherein the etch duration is calculated based on a known etch rate of the excess metal portion.

14. A method according to claim 1, wherein the step of plasma etching the excess metal portion comprises preferentially etching the excess metal portion along a direction substantially transverse to the metal interconnection layer.

15. An integrated circuit obtainable by a method according to claim 1.