SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20200135493A1
• Filed: 12/26/2019
• Published: 04/30/2020
• Est. Priority Date: 02/18/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHAO, Yuan-Shun, KUO, Chih-Wei
• Granted Patent: US 11,101,143 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

Claims

1. A source/drain structure of an n-type semiconductor field effect transistor, the source/drain structure comprising:

an epitaxial layer formed over a base semiconductor layer; and

an alloy layer of Si, Ge and Ti disposed over the epitaxial layer.

2. The source/drain structure of claim 1, wherein the epitaxial layer is made of Si containing P.

3. The source/drain structure of claim 2, wherein an amount of phosphorous in the epitaxial layer is in a range from 1×

10²⁰ cm<sup>−

3</sup> to 5×

10²¹ cm<sup>−

3</sup>.

4. The source/drain structure of claim 2, wherein the alloy layer is in contact with the epitaxial layer.

5. The source/drain structure of claim 2, wherein the epitaxial layer includes a first layer and a second layer having different phosphorous concentration from each other.

6. The source/drain structure of claim 5, wherein an amount of phosphorous in the first layer is smaller than an amount of phosphorous in the second layer.

7. The source/drain structure of claim 6, wherein the amount of phosphorous in the first layer is in a range from 2×

10²⁰ cm<sup>−

3</sup> to 7×

10²⁰ cm<sup>−

3</sup>, and the amount of phosphorous in the second layer is in a range from 3×

10²⁰ cm<sup>−

3</sup> to 4×

10²¹ cm<sup>−

3</sup>.

8. A source/drain structure of an n-type semiconductor field effect transistor, the source/drain structure comprising:

an epitaxial layer formed over a base semiconductor layer;

a SiGe layer disposed over the epitaxial layer, and

an alloy layer of Si, Ge and Ti disposed over the epitaxial layer.

9. The source/drain structure of claim 8, wherein the epitaxial layer is made of Si containing P.

10. The semiconductor device of claim 9, wherein the alloy layer is disposed over the SiGe layer.

11. The semiconductor device of claim 9, wherein:

the SiGe layer is disposed on the epitaxial layer, and

the alloy layer is disposed on the epitaxial layer.

12. The semiconductor device of claim 8, wherein the SiGe layer is a S_1-xGe_x layer, where x is in a range from 0.25 to 0.5.

13. The semiconductor device of claim 12, wherein the SiGe layer further contains phosphorous.

14. The semiconductor device of claim 13, wherein an amount of phosphorus in the Si_1-xGe_x layer is in a range from 1×

10²⁰ cm<sup>−

3</sup> to 5×

10²¹ cm<sup>−

3</sup>.

15. An n-type semiconductor field effect transistor (FET), comprising:

an isolation insulating layer disposed over a substrate;

fin structures disposed over the substrate, upper portions of the fin structures being exposed from the isolation insulating layer; and

a merged source/drain structure formed on the upper portions of the fin structure,

wherein the merged source/drain structure includes a SiP layer, and an alloy layer of Si, Ge and Ti.

16. The n-type FET of claim 15, further comprising a source/drain contact disposed in an interlayer dielectric layer and contacting the alloy layer.

17. The n-type FET of claim 15, wherein the alloy layer further comprises phosphorous.

18. The n-type FET of claim 15, the SiP layer includes a first SiP layer and a second SiP layer having different phosphorous concentration from each other.

19. The n-type FET of claim 16, wherein an amount of phosphorous in the first SiP layer is smaller than an amount of phosphorous in the second SiP layer.

20. The n-type FET of claim 16, wherein a thickness of the first SiP layer is smaller than a thickness of the second SiP layer.