Multi Integrated Circuit Chip Carrier Package

• US 20200135495A1
• Filed: 10/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Interrante, Marcus E., Lange, Kathryn R., Sikka, Kamal K., Sinha, Tuhin, Toy, Hilton T., Zitz, Jeffrey A.
• Granted Patent: US 10,978,314 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/32 Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/4006 with bolts or screws
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/4338 Pistons, e.g. spring-loaded members
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates

Abstract

A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.

Claims

1. An electronic device fabrication method comprising:

positioning a multiple IC chip carrier against a carrier deck that comprises a plurality of first alignment features;

aligning a lid, comprising a plurality of second alignment features, with the carrier deck by engaging the first alignment features with the second alignment features;

connecting the lid to each IC chip of the multiple IC chip carrier; and

removing the multiple IC chip carrier from the carrier deck.

2. The method of claim 1, further comprising:

connecting the lid to the multiple IC chip carrier

3. The method of claim 2, further comprising:

applying a seal band material upon the multiple IC chip carrier around a circumference of each IC chip or applying a seal band material upon an underside surface of the lid.

4. The method of claim 2, further comprising:

applying a thermal interface material upon an upper surface of each IC chip of the multiple IC chip carrier.

5. The method of claim 2, further comprising:

applying a thermal interface material upon an underside surface of the lid.

6. The method of claim 2, further comprising:

curing a seal band that exists between the lid and the multiple IC chip carrier; and

curing thermal interface material that exists between the lid and each IC chip of the multiple IC chip carrier.

7. The method of claim 6, further comprising:

compressing the lid against the multiple IC chip carrier by applying a force from a fixture cover against the lid towards the carrier deck; and

removing the fixture cover from the lid, subsequent to curing the seal band and subsequent to curing the thermal interface material.

8. The method of claim 7, wherein compressing the lid against the multiple IC chip carrier flattens the multiple IC chip carrier.

9. The method of claim 1, further comprising:

connecting a heatsink to the lid upper surface.

10. The method of claim 1, further comprising:

connecting the multiple IC chip carrier bottom surface to a motherboard.

11. A multiple integrated circuit (IC) chip carrier package fabrication system comprising:

a carrier deck comprising a plurality of first alignment features;

a multiple IC chip carrier positioned against the carrier deck, the multiple IC chip carrier comprising multiple IC chips; and

a lid comprising a plurality of second alignment features, wherein the plurality of first alignment features engage with the plurality of second alignment features.

12. The system of claim 11, wherein the lid is connected to the multiple IC chips and wherein the lid is connected to the multiple IC chip carrier.

13. The system of claim 12, further comprising:

a fixture cover connected to the lid upper surface and moveable towards the carrier deck to compress the lid against the multiple IC chip carrier and to compress the lid against the multiple IC chips.

14. The system of claim 12, further comprising:

a seal band material between the multiple IC chip carrier and the lid; and

thermal interface material between each IC chip and the lid.

15. The system of claim 12, wherein one or more of the multiple IC chips is connected to the multiple IC chip carrier in a landscape orientation and wherein one or more of the multiple IC chips is connected to the multiple IC chip carrier in a portrait orientation.

16. A multiple IC chip carrier package fabrication method comprising:

positioning a convex multiple IC chip carrier against a carrier deck that comprises a plurality of first alignment features;

aligning a lid, comprising a plurality of second alignment features, with the carrier deck by engaging the plurality of first alignment features with the plurality of second alignment features; and

compressing the convex multiple IC chip carrier and the lid by applying a compressive force between the carrier deck and a fixture cover that is connected to the lid upper surface.

17. The method of claim 16, wherein compressing the convex multiple IC chip carrier and the lid flattens the convex multiple IC chip carrier.

18. The method of claim 17, wherein compressing the convex multiple IC chip carrier and the lid comprises:

attaching the lid to each IC chip of the multiple IC chip carrier.

19. The method of claim 17, wherein compressing the convex multiple IC chip carrier and the lid comprises:

attaching the lid to the multiple IC chip carrier.

20. The method of claim 17, further comprising:

removing the fixture cover from the lid upper surface

removing the flattened multiple IC chip carrier from the carrier deck.