CARRIER SUBSTRATE AND PACKAGING METHOD USING THE SAME

• US 20200135498A1
• Filed: 05/29/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KO, Ji-Han, KIM, Wonkeun
• Granted Patent: US 11,211,273 B2
• Time in Patent Office: Days
• CPC Class Codes: B32B 17/06 comprising glass as the main or only constituent of a layer, next to another layer of a specific material
• CPC Class Codes: C03C 27/048 consisting of an adhesive specially adapted for that purpose
• CPC Class Codes: C03C 27/06 Joining glass to glass by processes other than fusing fusing C03B23/20; units for use as elements for closing wall or like openings and comprising two or more parallel glass panes in spaced relationship, the panes being permanently secured together E06B3/66
• CPC Class Codes: C03C 27/10 with the aid of adhesive specially adapted for that purpose
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/673 using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders holders for supporting a complete device in operation H01L23/32
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83862 Heat curing
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A carrier substrate and a packaging method, the carrier substrate including a first layer; a second layer; and a first glue layer between the first layer and the second layer, wherein the first glue layer is removably attached to the first layer.

Claims

1. A carrier substrate, comprising:

a first layer;

a second layer; and

a first glue layer between the first layer and the second layer,

wherein the first glue layer is removably attached to the first layer.

2. The carrier substrate as claimed in claim 1, wherein a coefficient of thermal expansion of the first layer is different from a coefficient of thermal expansion of the second layer.

3. The carrier substrate as claimed in claim 2, wherein the coefficient of thermal expansion of the first layer is greater than the coefficient of thermal expansion of the second layer.

4. The carrier substrate as claimed in claim 3, wherein:

the second layer includes glass, and

the first layer includes metal.

5. The carrier substrate as claimed in claim 3, further comprising:

a third layer; and

a second glue layer between the second layer and the third layer,

wherein the second glue layer is removably attached to the second layer.

6. The carrier substrate as claimed in claim 5, wherein the coefficient of thermal expansion of the second layer is greater than a coefficient of thermal expansion of the third layer.

7. The carrier substrate as claimed in claim 6, wherein:

the third layer includes glass,

the second layer includes metal, and

the first layer includes an organic material.

8. A packaging method, comprising:

preparing a carrier substrate such that the carrier substrate includes a first layer and a second layer on the first layer;

performing a first process on the carrier substrate; and

removing the second layer from the first layer.

9. The packaging method as claimed in claim 8, wherein performing the first process includes:

placing a semiconductor chip on the first layer;

heating the semiconductor chip; and

cooling the semiconductor chip.

10. The packaging method as claimed in claim 8, wherein a coefficient of thermal expansion of the second layer is less than a coefficient of thermal expansion of the first layer.

11. The packaging method as claimed in claim 8, wherein the carrier substrate further includes a third layer on the second layer.

12. The packaging method as claimed in claim 11, further comprising:

removing the third layer from the second layer; and

performing a second process on the carrier substrate.

13. The packaging method as claimed in claim 12, wherein performing the second process includes:

forming a molding layer covering a semiconductor chip on the first layer; and

cooling the semiconductor chip and the molding layer.

14. The packaging method as claimed in claim 12, wherein a coefficient of thermal expansion of the third layer is less than a coefficient of thermal expansion of the second layer.

15. A packaging method, comprising:

preparing a carrier substrate such that the carrier substrate includes a first layer;

performing a first process on the carrier substrate; and

adding a second layer onto the first layer.

16. The packaging method as claimed in claim 15, wherein performing the first process includes placing and heating a semiconductor chip on the first layer.

17. The packaging method as claimed in claim 15, wherein a coefficient of thermal expansion of the second layer is greater than a coefficient of thermal expansion of the first layer.

18. The packaging method as claimed in claim 15, further comprising:

performing a second process on the carrier substrate; and

adding a third layer onto the second layer.

19. The packaging method as claimed in claim 18, wherein performing the second process includes molding and heating a semiconductor chip on the first layer.

20. The packaging method as claimed in claim 18, wherein a coefficient of thermal expansion of the third layer is greater than a coefficient of thermal expansion of the second layer.