ELECTROMIGRATION EVALUATION METHODOLOGY WITH CONSIDERATION OF THERMAL AND SIGNAL EFFECTS

• US 20200135514A1
• Filed: 09/06/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSENG, Hsien Yu, LIU, Sheng-Feng
• Granted Patent: US 11,107,714 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/67248 Temperature monitoring

Abstract

A method for evaluating a heat sensitive structure involving identifying a heat sensitive structure in an integrated circuit design layout, the heat sensitive structure characterized by a nominal temperature, identifying a heat generating structure within a thermal coupling range of the heat sensitive structure, calculating an operating temperature of the first heat generating structure; calculating a temperature increase or the heat sensitive structure induced by thermal coupling to the heat generating structure at the operating temperature; and performing an electromigration (EM) analysis of the heat sensitive structure at an evaluation temperature obtained by adjusting the nominal temperature by the temperature increase induced by the heat generating structure.

Claims

1. A method for evaluating a heat sensitive structure comprising:

identifying a heat sensitive structure in an integrated circuit design layout, the heat sensitive structure having a nominal temperature T_nom;

identifying a first signal carrying structure within a thermal coupling range of the heat sensitive structure;

calculating an operating temperature T_oph1 of the first signal carrying structure as a function of an electrical signal current applied to the first signal carrying structure over a time period t;

calculating a temperature increase Δ

T_hi for the heat sensitive structure induced by thermal coupling to the first signal carrying at the operating temperature T_oph1;

performing an electromigration (EM) analysis of the heat sensitive structure at an evaluation temperature T_E=T_nom+T_h;

verifying that the EM analysis of the heat sensitive structure meets a design specification; and

generating a tape out corresponding to the integrated circuit design layout for manufacturing a semiconductor device.

2. The method according to claim 1, further comprising:

identifying a second heat generating structure within a thermal coupling range of the heat sensitive structure;

calculating an operating temperature T_oph2 for the second heat generating structure;

calculating a Δ

T_h2 for the heat sensitive structure induced by thermal coupling to the second heat generating structure at the operating temperature T_oph2; and

evaluating the heat sensitive structure at the evaluation temperature T_E=T_nom+Δ

T_h1+Δ

T_h2.

3. The method according to claim 1, wherein:

the heat sensitive structure comprises a conductive line.

4. The method according to claim 1, wherein:

the first signal carrying structure is a fin field effect transistor (FinFET) structure.

5. The method according to claim 2, wherein:

the second heat generating structure is a high-resistance (Hi-R) structure.

6. The method according to claim 1, wherein calculating an operating temperature T_oph1 of the first signal carrying structure further comprises:

calculating the electrical signal current as a function of the waveform, frequency, and duty cycle of an electrical signal applied to the first signal carrying structure over the time period t.

7. The method according to claim 1, further comprising:

identifying a first heat sink element within a thermal coupling range of the heat sensitive structure;

calculating an operating temperature T_opc1 for the first heat sink element;

calculating a Δ

T_c1 for the heat sensitive structure induced by thermal coupling to the first heat sink element at the operating temperature T_opc2; and

evaluating the heat sensitive structure at the evaluation temperature T_E=T_nom+Δ

T_h1Δ

T_h2+Δ

T_c1.

8. The method according to claim 1, further comprising:

verifying that the evaluation of the heat sensitive structure meets design specifications; and

manufacturing a semiconductor device in response to the heat sensitive structure meeting the design specifications.

9. A method for evaluating a heat sensitive structure of in an integrated circuit design comprising:

identifying a heat sensitive structure;

calculating a nominal temperature T. of the heat sensitive structure;

identifying a first heat dissipating structure within a first thermal coupling range of the heat sensitive structure;

calculating an operating temperature T_opcl of the heat dissipating structure;

calculating a Δ

T_c1 for the heat sensitive structure induced by thermal coupling with the T_opc1 of the heat dissipating structure;

conducting an electromigration (EM) performance evaluation of the heat sensitive structure at an evaluation temperature T_E=T_nom+Δ

T_c1,

verifying that the EM analysis of the heat sensitive structure meets a design specification; and

generating a tape out corresponding to the integrated circuit design layout for manufacturing a semiconductor device.

10. The method according to claim 9, further comprising:

identifying a second heat dissipating structure within a second thermal coupling range of the heat sensitive structure;

calculating an operating temperature T_opc2 for the second heat dissipating structure;

calculating a Δ

T_c2 for the heat sensitive structure induced by thermal coupling to the second heat dissipating structure at the operating temperature T_opc2; and

conducting the evaluation of the heat sensitive structure at the evaluation temperature T_E=T_nom+Δ

T_c1+Δ

T_c2.

11. The method according to claim 9, wherein:

the heat sensitive structure is a FinFET device.

12. The method according to claim 10, wherein:

the first thermal coupling range and the second thermal coupling range are different.

13. The method according to claim 10, wherein:

calculating the nominal temperature T_nom comprises an analysis of self-heating effect Δ

T for the heat sensitive structure and environmental temperature conditions T_env, with T_nom=T_env+Δ

T.

14. The method for evaluating a heat sensitive structure of an integrated circuit design according to claim 9, wherein:

the first heat dissipating structure is an active region.

15. The method according to claim 9, wherein:

the first heat dissipating structure is a portion of an electrically conductive pattern.

16. The method according to claim 9, further comprising:

retrieving design data corresponding to the integrated circuit design from a database of integrated circuit designs; and

analyzing the design data to identify the heat sensitive structure and the first heat dissipating structure.

17. The method according to claim 10, further comprising:

identifying a plurality of conductive layers in the integrated circuit design; and

retrieving a plurality of thermal coefficients associated with each of the plurality of conductive layers, wherein the thermal coefficients comprise a de-rating coefficient, a layer effect, and a temperature profile.

18. A system for evaluating a heat sensitive structure of an integrated circuit design comprising:

a memory configured for maintaining integrated circuit design layout data, thermal data, process data, and operational parameters corresponding to the integrated circuit design;

a processor configured for accessing the memory and analyzing the integrated circuit design layout data to identify a heat sensitive structure having a nominal temperature Tnom;

a first heat generating structure within a first thermal coupling range of the heat sensitive structure; and

a heat dissipating structure within a second thermal coupling range of the heat sensitive structure;

the processor being further configured for

calculating Δ

T_h for the heat sensitive structure induced by thermal coupling with the heat generating structure;

calculating a Δ

T_c for the heat sensitive structure induced by thermal coupling with the heat dissipating structure; and

conducting an electromigration (EM) evaluation of the heat sensitive structure at an adjusted temperature T_E=T_nom+Δ

T_h+Δ

T_c; and

a network interface configured for transmitting the results of the EM evaluation for a design review.

19. The system according to claim 18,

wherein the first thermal coupling range and the second thermal coupling range are not identical.

20. The system according to claim 18, wherein:

the processor being further configured for determining whether the integrated circuit design layout passes the EM analysis; and

generating a new tape out file for manufacture of a semiconductor device according to the integrated circuit design in response to the integrated circuit design layout passing the EM analysis.