METAL SPACER SELF ALIGNED DOUBLE PATTERNING WITH AIRGAP INTEGRATION

• US 20200135537A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Hsueh-Chung, Kelly, James, Mignot, Yann, Peethala, Cornelius Brown, Clevenger, Lawrence A.
• Granted Patent: US 10,811,310 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53228 the principal metal being copper

Abstract

A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.

Claims

1. A method of forming an interconnect structure, the method comprising:

forming sidewall spacers on a plurality of mandrels that are overlying an intermetal dielectric layer, wherein the sidewall spacers comprise a metal and define metal lines, wherein the plurality of mandrels comprises amorphous silicon;

removing the plurality of mandrels;

depositing a dielectric liner layer;

depositing an ultra-low k dielectric layer and forming one or more airgaps between at least one pair of adjacent sidewall spacers;

planarizing the ultralow k dielectric layer to form a top planar surface;

etching the ultralow k dielectric to form via openings self-aligned to one or more of the metal lines; and

filling the via openings with copper.

2. The method of claim 1, wherein removing the plurality of mandrels comprises a wet etch process.

3. The method of claim 1, wherein the sidewall spacers comprise cobalt, ruthenium, tantalum, tungsten, aluminum, rhodium, platinum, nickel, silver, gold, or combinations thereof.

4. The method of claim 1, wherein forming the sidewall spacers on the plurality of mandrels comprises a self-aligned double patterning process.

5. The method of claim 1, wherein the ultra-low k dielectric has a k constant of less than 3.0

6. The method of claim 1, wherein the ultra-low k dielectric comprises porous organic silicate glasses, porous polyamide nanofoams, silica xerogels, porous hydrogen silsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous inorganic materials, porous CVD materials, porous organic materials, or combinations thereof.

7. The method of claim 1, wherein the metal lines comprise cobalt.

8. (canceled)

9. A method of forming an interconnect structure, the method comprising:

providing a mandrel pattern overlying a dielectric layer, wherein the mandrel pattern comprises amorphous silicon;

conformally depositing a metal onto the mandrel pattern;

etching back a portion of the metal to the mandrel pattern to form metal spacers on sidewalls of the mandrel pattern;

removing the mandrel pattern to define a plurality of metal lines from the metal spacers;

lithographically defining a final metal pattern from the plurality of metal lines;

depositing a dielectric layer and forming a least one airgap between one or more adjacent metal lines;

depositing an ultra-low k dielectric layer;

planarizing the ultra-low k dielectric layer;

applying a single damascene process to form a via opening self-aligned to one or more of the metal lines; and

filling the via opening with a metal to form an electrical connection with the one or more metal lines.

10. The method of claim 9, wherein the sidewall spacers and the filled via opening comprise cobalt, ruthenium, tantalum, tungsten, aluminum, rhodium, platinum, nickel, silver, gold, or combinations thereof.

11. The method of claim 9, wherein the sidewall spacers and the metal lines comprise cobalt.

13. The method of claim 9, wherein the ultra-low k dielectric has a k constant of less than 3.0

14. The method of claim 9, wherein the ultra-low k dielectric comprises porous organic silicate glasses, porous polyamide nanofoams, silica xerogels, porous hydrogen silsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous inorganic materials, porous CVD materials, porous organic materials, or combinations thereof.

12. (canceled)

15-25. -25. (canceled)