CROSSBAR REINFORCED SEMICONDUCTOR FINS HAVING REDUCED WIGGLING

• US 20200135539A1
• Filed: 10/25/2018
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Liu, Chi-Chun, Mignot, Yann, Sankarapandian, Muthumanickam
• Granted Patent: US 10,755,963 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76208 using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for forming a silicon structure. A non-limiting example of the method includes forming at least two semiconductor fins on a substrate. A polymer brush material is formed over the fins and the substrate. A block copolymer (BCP) composed of a first polymer and a second polymer which are covalently bound together is applied over the polymer brush material, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins. The first microdomains are composed of the first polymer and the second microdomains are composed of the second polymer. The second microdomains can be selectively removed.

Claims

1. A method for forming a semiconductor structure, the method comprising:

forming at least two semiconductor fins on a substrate;

forming a monolayer of polymer brush material over the fins and the substrate;

applying a block copolymer comprising a first polymer and a second polymer in between the fins, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins, the first microdomains comprising the first polymer and the second microdomains comprising the second polymer; and

removing the second microdomains.

2. The method of claim 1, wherein the first polymer is polystyrene and the second polymer is poly(methyl methacrylate) (PMMA).

3. The method of claim 1, wherein the polymer brush has about 60% of styrene content and the block copolymer is lamella-forming with about 50% of polystyrene.

4. The method of claim 1 further comprising applying a silicon nitride liner over the first fins prior to forming the polymer brush material.

5. The method of claim 4 further comprising depositing an oxide over the silicon nitride liner at the bottom of the trench and the top of the fins.

6. The method of claim 1 further comprising, after removing the second microdomains, etching the oxide and silicon nitride liner to expose the bottom of the silicon trench.

7. The method of claim 6 further comprising etching the silicon crossbars and selectively removing the oxide template at the bottom of the trench to expose silicon crossbars.

8. The method of claim 7 further comprising implanting material in the exposed silicon crossbars to damage the exposed silicon crossbars.

9. The method of claim 8, wherein the exposed silicon crossbars are partially converted from crystalline silicon to polycrystalline or amorphous silicon.

10. The method of claim 7 further comprising oxidizing the exposed silicon crossbars into thermal oxide.

11. The method of claim 10, wherein oxidizing occurs through an annealing process.

12. The method of claim 7 further comprising performing a shallow trench isolation (STI) fill between the fins by flowable oxide before the oxidation.

13. The method of claim 12 further comprising performing a thermal cure.

14. A semiconductor structure comprising:

a substrate;

semiconductor fins on the substrate with trenches between the fins; and

spaced apart silicon crossbars within the trenches between the fins and perpendicular to the fins.

15. The semiconductor structure of claim 14, wherein the silicon crossbars comprise silicon oxide having a first density.

16. The semiconductor structure of claim 15 further comprising a shallow trench isolation (STI) oxide over the semiconductor fins and the silicon crossbars.

17. The semiconductor structure of claim 16, wherein the STI oxide has a second density less than the first density of the silicon oxide.

18. The semiconductor structure of claim 17, wherein the silicon oxide is formed from damaged amorphous silicon.

19. The semiconductor structure of claim 17, wherein the silicon oxide is formed from undamaged crystalline silicon.

20. A method for forming a semiconductor structure, the method comprising:

forming at least two semiconductor fins on a substrate;

forming a monolayer of polymer brush material over the fins and the substrate;

applying a block copolymer comprising a first polymer and a second polymer in between the fins, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins, the first microdomains comprising the first polymer and the second microdomains comprising the second polymer; and

removing the second microdomains, wherein the polymer brush is greater than about 47% and less than about 78% of styrene content and the block copolymer is lamella-forming with about 50% of polystyrene.