SEMICONDUCTOR STRUCTURE INCLUDING ISOLATIONS

• US 20200135540A1
• Filed: 12/20/2019
• Published: 04/30/2020
• Est. Priority Date: 11/09/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LO, WEN-SHUN, CHANG, YU-CHI, TSUI, FELIX YING-KIT
• Granted Patent: US 10,964,586 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

Claims

1. A semiconductor structure comprising:

a substrate comprising a first region and a second region defined thereon, wherein the substrate comprises a first material;

a first isolation comprising a first width in the first region;

a second isolation comprising a second width in the second region; and

a region surrounding the first isolation in the substrate and comprising the first material and a second material,

wherein the first width is greater than the second width, a bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

2. The semiconductor structure of claim 1, wherein the first material comprises silicon (Si), and the second material comprises germanium (Ge), nitrogen (N) or argon (Ar).

3. The semiconductor structure of claim 1, wherein the second material has an atomic mass greater than an atomic mass of the first material.

4. The semiconductor structure of claim 1, wherein a ratio of the first width of the first isolation over the second width of the second isolation is between about 50 and about 100.

5. The semiconductor structure of claim 1, wherein the second isolation comprises a divot around a top corner, and the first isolation comprises a divot-free top corner.

6. The semiconductor structure of claim 1, wherein the first isolation and the second isolation respectively comprise a divot-free top corner.

7. The semiconductor structure of claim 1, wherein a topmost surface of the first isolation and a topmost surface of the second isolation are higher than a surface line of the substrate.

8. A semiconductor structure comprising:

a substrate comprising a first region and a second region defined thereon, wherein the substrate comprises a first material;

a first isolation in the first region and comprising a first upper portion above a surface line of the substrate and a first lower portion under the surface line of the substrate;

a second isolation in the second region and comprising a second upper portion above the surface line of the substrate and a second lower portion under the surface line of the substrate; and

a region surrounding the first isolation in the substrate and comprising the first material and a second material,

wherein a width of the first upper portion is substantially the same as a width of the first lower portion, and a width of the second upper portion is less than a width of the second lower portion.

9. The semiconductor structure of claim 8, wherein the region is in contact with sidewalls and a bottom surface of the first lower portion.

10. The semiconductor structure of claim 8, wherein the first material comprises silicon (Si), and the second material comprises germanium (Ge), nitrogen (N) or argon (Ar).

11. The semiconductor structure of claim 8, wherein the second material has an atomic mass greater than an atomic mass of the first material.

12. The semiconductor structure of claim 8, wherein the width of the first lower portion is greater than the width of the second lower portion.

13. The semiconductor structure of claim 8, wherein the second isolation comprises a divot formed by the second upper portion and the second lower portion.

14. The semiconductor structure of claim 12, further comprising a first gate structure covering the first isolation and a second gate structure covering the second isolation, wherein the divot is filled with the second structure.

15. The semiconductor structure of claim 8, wherein the first isolation comprises a divot-free top corner.

16. The semiconductor structure of claim 8, wherein a topmost surface of the first isolation and a topmost surface of the second isolation are higher than a surface line of the substrate.

17. A semiconductor structure comprising:

a substrate comprising a first region and a second region defined thereon, wherein the substrate comprises a first material;

a first isolation in the first region;

a second isolation in the second region;

a region surrounding the first isolation in the substrate and comprising the first material and a second material;

a first gate structure covering the first isolation; and

a second gate structure covering the second isolation,

wherein the second isolation comprises a divot around a top corner, the first isolation comprises a divot-free top corner, and the divot of the second isolation is filled with the second gate structure.

18. The semiconductor structure of claim 17, wherein the first material comprises silicon (Si), and the second material comprises germanium (Ge), nitrogen (N) or argon (Ar), and the second material has an atomic mass greater than an atomic mass of the first material.

19. The semiconductor structure of claim 17, wherein the first isolation has a first width, the second isolation has a second width, and a ratio of the first width over the second width is between about 50 and about 100.

20. The semiconductor structure of claim 17, wherein a topmost surface of the first isolation and a topmost surface of the second isolation are higher than a surface line of the substrate.