SELECTIVE DEPOSITION OF DIELECTRICS ON ULTRA-LOW K DIELECTRICS

• US 20200135544A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shobha, Hosadurga, Wojtecki, Rudy J., Arellano, Noel, De Silva, Ekmini A.
• Granted Patent: US 10,692,755 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02107 Forming insulating materials on a substrate
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric

Abstract

A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a via in a first dielectric layer arranged on a metal layer, the via exposing a portion of the metal layer;

forming a trench in the first dielectric layer;

forming a self-assembled monolayer on the portion of the metal layer exposed by an opening in the via; and

depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.

2. The method of claim 1, wherein the dielectric layer has a k value of about 1.8 to about 4.0.

4. The method of claim 1 further comprising removing the self-assembled monolayer from the portion of the metal layer exposed by the opening.

5. The method of claim 1, wherein the trench stops within the first dielectric layer.

6. The method of claim 1, wherein depositing the second dielectric layer comprises depositing a precursor with a higher inherent reactivity on the first dielectric layer compared to the metal layer.

7. The method of claim 1, wherein the second dielectric layer comprises SiO₂, SiN, SiOC, hydrogenated silicon carbon oxide (SiCOH), SiCH, SiCNH, high density plasma oxide, borophosphosilicate glass (BPSG), TiO₂, TiSiO, ZrO, ZnO, or Al₂O₃.

3. (canceled)

8. A method of fabricating a semiconductor device, the method comprising:

forming an opening through a metal layer and a first dielectric layer;

forming a self-assembled monolayer on exposed surfaces of the metal layer; and

depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the opening and is selectively deposited onto the first dielectric layer.

9. The method of claim 8, wherein the first dielectric layer has a k value of about 1.8 to about 4.0.

11. The method of claim 8 further comprising, subsequent to depositing the second dielectric layer, removing the self-assembled monolayer from the metal layer.

12. The method of claim 8 further comprising, subsequent to depositing the second dielectric layer, forming a second opening in the metal layer.

13. The method of claim 8, wherein depositing the second dielectric layer comprises depositing a precursor with a higher inherent reactivity on the first dielectric layer compared to the metal layer.

10. (canceled)

14. A semiconductor device comprising:

an opening within a first dielectric layer that extends to and exposes a portion of a metal layer;

a self-assembled monolayer on portion of the metal layer that is exposed by the opening; and

a second dielectric layer selectively contacting the first dielectric layer and lining sidewalls of the trench.

15. The semiconductor device of claim 14, wherein the first dielectric layer has a k value of about 1.8 to about 4.0.

17. The semiconductor device of claim 14 further comprising a metal filling the opening.

18. The semiconductor device of claim 14 further comprising a second opening in the first dielectric layer.

19. The semiconductor device of claim 18, wherein the second opening stops in the first dielectric layer.

20. The semiconductor device of claim 19, wherein the second dielectric layer is also deposited onto sidewalls of the second opening.

16. (canceled)