SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

• US 20200135547A1
• Filed: 12/03/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien
• Granted Patent: US 11,121,026 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of patterning openings for conductive contacts in a target layer of a semiconductor device and methods of forming conductive contacts. The method of patterning openings may be used to form contact openings in an inter-layer dielectric (ILD) layer of a semiconductor substrate for contacts to source/drain regions of FinFET devices. A hard mask layer may be patterned to form a cut mask by transferring slotted openings of a first middle layer of a tetra-layer photoresist and a cut MD pattern of a photoresist layer formed over the first middle layer of the tetra-layered photoresist using photolithography techniques. Once the cut mask is formed, contact openings are formed within the ILD layer down to the source/drain regions of the FinFET devices of the semiconductor substrate. The contact openings may be filled with conductive material(s) to define conductive contacts (e.g., conductive plugs).

Claims

1. A method comprising:

depositing a first mask layer over a target layer;

forming a tetra-layer photoresist over the first mask layer;

transferring a slot pattern of a first photoresist layer of the tetra-layer photoresist into a first middle layer of the tetra-layer photoresist;

forming a cut pattern of an etch mask photoresist layer over the slot pattern of the first middle layer;

transferring the cut pattern into a bottom layer of the tetra-layer photoresist;

transferring the slot pattern and the cut pattern of the bottom layer into the first mask layer; and

etching the target layer using the slot pattern and the cut pattern of the first mask layer to form contact openings in the target layer.

2. The method according to claim 1, further comprising:

depositing a second photoresist layer over the first middle layer, after transferring the slot pattern of the first photoresist layer into the first middle layer; and

transferring a second slot pattern of the second photoresist layer into the first middle layer of the tetra-layer photoresist, the second slot pattern being an overlap shift of the first slot pattern.

3. The method according to claim 2, wherein the transferring the slot pattern of the first photoresist layer into the first middle layer of the tetra-layer photoresist further comprises exposing first surfaces of a second middle layer of the tetra-layer photoresist.

4. The method according to claim 3, wherein the first middle layer of the tetra-layer photoresist comprises a silicon oxynitride material.

5. The method according to claim 4, wherein the second middle layer of the tetra-layer photoresist comprises a metal oxide material.

6. The method according to claim 4, wherein the first middle layer is etched using a process gas comprising:

a fluorine-containing gas selected from the group consisting of CF₄, NF₃, and combinations thereof; and

a polymer-forming gas selected from the group consisting of CHF₃, CH₂F₂, CH₃F, C₄F₆, C₄F₈, and combinations thereof.

7. The method according to claim 1, wherein the target layer includes an inter-dielectric layer disposed on a semiconductor structure, the semiconductor structure including a plurality of semiconductor fins.

8. The method according to claim 1, further comprising filling the openings in the target layer with a conductive material.

9. A method comprising:

forming a series of slotted openings in a first middle layer of a compound photoresist layer disposed over a semiconductor structure;

forming a patterned etching mask including a plurality of photoresist cut islands in a second photoresist layer disposed over the series of slotted openings in the first middle layer of the compound photoresist layer, the plurality of photoresist cut islands spanning across and filling a portion of one or more of the series of slotted openings in the first middle layer;

transferring the series of slotted openings and the patterned etching mask into a bottom layer of the compound photoresist layer to form a cut mask; and

using the cut mask to form contact openings through an inter-layer dielectric (ILD) layer disposed over the semiconductor structure, the contact openings exposing portions of source and drain regions of devices disposed within the semiconductor structure.

10. The method of claim 9, wherein the forming the series of slotted openings in the first middle layer of the compound photoresist layer comprises forming a first series of slotted openings in the first middle layer.

11. The method of claim 10, wherein the forming the series of slotted openings in the first middle layer of the compound photoresist layer comprises, after the forming the first series of slotted openings, forming a second series of slotted openings in the first middle layer, the second series of slotted openings being shifted from the series of the first slotted openings.

12. The method of claim 9, wherein the forming the patterned etching mask in the bottom layer of the compound photoresist layer comprises using a hard mask layer disposed between the bottom layer of the compound photoresist layer and the inter-layer dielectric layer as an etch stop layer for the bottom layer of the compound photoresist layer.

13. The method of claim 12, wherein a material of the hard mask layer is a material selected from the group consisting of tungsten carbide and titanium nitride.

14. The method of claim 12, wherein a first surface of the hard mask layer is in contact with the bottom layer of the compound photoresist layer and a second surface of the hard mask layer is in contact with the ILD layer, the second surface of the hard mask layer being opposite the first surface of the hard mask layer.

15. The method of claim 12, wherein forming the series of slotted openings in the first middle layer of the compound photoresist layer includes using a second middle layer of the compound photoresist layer as a stop layer over the bottom layer of the compound photoresist layer.

16. A method of forming contact plugs for FinFET devices, comprising:

depositing a hard mask layer over a semiconductor structure;

forming a tetra-layer photoresist layer over the hard mask layer;

etching a series of slotted openings in a first middle layer of the tetra-layer photoresist layer;

forming a patterned photoresist mask on remaining portions of the first middle layer;

transferring the patterned photoresist mask and the series of slotted openings into a bottom layer of the tetra-layer photoresist layer;

forming a cut mask in the hard mask layer using the patterned photoresist mask and the series of slotted openings in the bottom layer;

etching contact openings through an inter-layer dielectric (ILD) layer and to surfaces of source regions and drain regions of the FinFET devices disposed within the semiconductor structure; and

depositing a conductive material in the contact openings to form contact plugs for the FinFET devices.

17. The method of claim 16, wherein the depositing the hard mask layer over the semiconductor substrate comprises depositing the hard mask layer in contact with the ILD layer.

18. The method of claim 17, wherein the forming the tetra-layer photoresist layer over the hard mask layer comprises depositing a bottom layer of the tetra-layer photoresist layer over and in contact with a second surface of the hard mask layer.

19. The method of claim 16, wherein the forming the patterned photoresist mask comprises forming a plurality of photoresist cut islands over and in contact with two or more of the remaining portions of the first middle layer, the photoresist cut islands extending over one or more of the series of slotted openings disposed between the remaining portions of the first middle layer.

20. The method of claim 16, further comprising:

before the transferring the patterned photoresist mask and the series of slotted openings into the bottom layer, using a second middle layer of the tetra-layer photoresist layer as an etch stop layer for the etching of the series of slotted openings in the first middle layer.