SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
First Claim
1. A method comprising:
- depositing a first mask layer over a target layer;
forming a tetra-layer photoresist over the first mask layer;
transferring a slot pattern of a first photoresist layer of the tetra-layer photoresist into a first middle layer of the tetra-layer photoresist;
forming a cut pattern of an etch mask photoresist layer over the slot pattern of the first middle layer;
transferring the cut pattern into a bottom layer of the tetra-layer photoresist;
transferring the slot pattern and the cut pattern of the bottom layer into the first mask layer; and
etching the target layer using the slot pattern and the cut pattern of the first mask layer to form contact openings in the target layer.
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Accused Products
Abstract
Methods of patterning openings for conductive contacts in a target layer of a semiconductor device and methods of forming conductive contacts. The method of patterning openings may be used to form contact openings in an inter-layer dielectric (ILD) layer of a semiconductor substrate for contacts to source/drain regions of FinFET devices. A hard mask layer may be patterned to form a cut mask by transferring slotted openings of a first middle layer of a tetra-layer photoresist and a cut MD pattern of a photoresist layer formed over the first middle layer of the tetra-layered photoresist using photolithography techniques. Once the cut mask is formed, contact openings are formed within the ILD layer down to the source/drain regions of the FinFET devices of the semiconductor substrate. The contact openings may be filled with conductive material(s) to define conductive contacts (e.g., conductive plugs).
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Citations
20 Claims
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1. A method comprising:
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depositing a first mask layer over a target layer; forming a tetra-layer photoresist over the first mask layer; transferring a slot pattern of a first photoresist layer of the tetra-layer photoresist into a first middle layer of the tetra-layer photoresist; forming a cut pattern of an etch mask photoresist layer over the slot pattern of the first middle layer; transferring the cut pattern into a bottom layer of the tetra-layer photoresist; transferring the slot pattern and the cut pattern of the bottom layer into the first mask layer; and etching the target layer using the slot pattern and the cut pattern of the first mask layer to form contact openings in the target layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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forming a series of slotted openings in a first middle layer of a compound photoresist layer disposed over a semiconductor structure; forming a patterned etching mask including a plurality of photoresist cut islands in a second photoresist layer disposed over the series of slotted openings in the first middle layer of the compound photoresist layer, the plurality of photoresist cut islands spanning across and filling a portion of one or more of the series of slotted openings in the first middle layer; transferring the series of slotted openings and the patterned etching mask into a bottom layer of the compound photoresist layer to form a cut mask; and using the cut mask to form contact openings through an inter-layer dielectric (ILD) layer disposed over the semiconductor structure, the contact openings exposing portions of source and drain regions of devices disposed within the semiconductor structure. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of forming contact plugs for FinFET devices, comprising:
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depositing a hard mask layer over a semiconductor structure; forming a tetra-layer photoresist layer over the hard mask layer; etching a series of slotted openings in a first middle layer of the tetra-layer photoresist layer; forming a patterned photoresist mask on remaining portions of the first middle layer; transferring the patterned photoresist mask and the series of slotted openings into a bottom layer of the tetra-layer photoresist layer; forming a cut mask in the hard mask layer using the patterned photoresist mask and the series of slotted openings in the bottom layer; etching contact openings through an inter-layer dielectric (ILD) layer and to surfaces of source regions and drain regions of the FinFET devices disposed within the semiconductor structure; and depositing a conductive material in the contact openings to form contact plugs for the FinFET devices. - View Dependent Claims (17, 18, 19, 20)
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Specification