SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

• US 20200135548A1
• Filed: 01/16/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WEI, TZU-HUI, HUANG, CHIEN-HUA, TSAI, CHERNG-SHIAW, LEE, CHUNG-JU
• Granted Patent: US 10,998,225 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76822 Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure

Abstract

The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate having a metal pattern, and forming an etch stop layer over the substrate. The etch stop layer includes a first material. The method also includes forming a diffused area in the etch stop layer by diffusing a second material from the metal pattern to the etch stop layer, and forming an insulative layer over the etch stop layer. The diffused area includes a lower etch rate to a first etchant than the insulative layer. A semiconductor device is also provided.

Claims

1. A method for forming a semiconductor device, comprising:

providing a substrate having a metal pattern;

forming an etch stop layer over the substrate, wherein the etch stop layer includes a first material;

forming a diffused area in the etch stop layer by diffusing a second material from the metal pattern to the etch stop layer; and

forming an insulative layer over the etch stop layer, wherein the diffused area includes a lower etch rate to a first etchant than the insulative layer.

2. The method of claim 1, wherein forming the diffused area in the etch stop layer comprises:

treating the metal pattern with ultraviolet light or heat.

3. The method of claim 1, further comprising:

forming a through hole in the insulative layer with the first etchant, thereby exposing a portion of the diffused area without exposing any non-diffused area in the etch stop layer.

4. The method of claim 3, wherein forming the diffused area in the etch stop layer comprises:

setting a predetermined width for the diffused area, wherein the predetermined width is wider than a width of the through hole.

5. The method of claim 3, further comprising:

transforming the exposed portion of the diffused area into a region having a higher etch rate to a second etchant than the non-exposed portion of the diffused area.

6. The method of claim 5, wherein transforming the exposed portion comprises:

treating the exposed portion by plasma, UV light or vapor.

7. The method of claim 5, further comprising:

removing the region by the second etchant without removing the non-exposed portion of the diffused area.

8. A method for forming a semiconductor device, comprising:

providing a substrate having a metal pattern;

forming an etch stop layer over the substrate, wherein the etch stop layer is doped with a doping material;

forming an insulative layer over the etch stop layer;

forming a through hole in the insulative layer with a first etchant to expose a portion of the etch stop layer, wherein the etch stop layer has a lower etch rate to the first etchant than the insulative layer; and

transforming the exposed portion of the etch stop layer into a region having a higher etch rate to a second etchant than the non-exposed portion of the etch stop layer.

9. The method of claim 8, wherein transforming the exposed portion comprises:

treating the exposed portion by plasma, UV light or vapor.

10. The method of claim 8, wherein forming the through hole comprises:

setting a predetermined width for the through hole, wherein the predetermined width is narrower than a width of the metal pattern.

11. The method of claim 8, further comprising:

removing the region by the second etchant without removing the non-exposed portion of the etch stop layer.

12. The method of claim 8, wherein an etch rate ratio of the region to the non-exposed portion is at least 10.

13. A semiconductor device, comprising:

a substrate having a metal pattern;

an insulative layer over the substrate;

an etch stop layer between the substrate and the insulative layer; and

a through hole extending from a surface of the insulative layer to the metal pattern;

wherein the etch stop layer comprises a non-diffused area and a diffused area, and the through hole is surrounded by the diffused area and further surrounded by the non-diffused area.

14. The semiconductor device of claim 13, wherein the etch stop layer comprises aluminum oxide.

15. The semiconductor device of claim 13, wherein the diffused area comprises a material existing in the metal pattern and the non-diffused area is free from the material.

16. The semiconductor device of claim 13, wherein the through hole is filled with a conductive material, and the conductive material is surrounded by the diffused area.

17. The semiconductor device of claim 16, wherein the diffused area contacts with the metal pattern and the conductive material.

18. The semiconductor device of claim 16, wherein the diffused area has a lower etch rate to an etchant used to form the through hole than the non-diffused area.

19. The semiconductor device of claim 16, wherein the etch stop layer comprises two diffused areas separated by the non-diffused area.

20. The semiconductor device of claim 16, wherein the diffused area includes a width wider than a width of the metal pattern.