SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

• US 20200135549A1
• Filed: 02/22/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Joon Goo, Simka, Harsono, Rodder, Mark Stephen
• Granted Patent: US 10,825,723 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry

Abstract

In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first conductive layer over a substrate;

forming an insulating layer on the first conductive layer;

forming a via through the insulating layer to expose the first conductive layer;

forming a self-assembled monolayer (SAM) over the insulating layer, a sidewall of the via, and a bottom of the via in contact with the first conductive layer;

removing a first portion of the SAM over the insulating layer, while leaving a second portion of the SAM at the sidewall of the via and the bottom of the via;

removing the SAM from the sidewall of the via, while leaving the SAM at the bottom of the via;

forming a barrier layer at the sidewall of the via;

removing the SAM from the bottom of the via to expose the first conductive layer; and

forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

2. The method of claim 1, further comprising, after forming the SAM over the insulating layer, the sidewall of the via, and the bottom of the via, forming a sacrificial layer over the SAM.

3. The method of claim 2, wherein the sacrificial layer comprises an organic material.

4. The method of claim 2, further comprising removing a first portion of the sacrificial layer outside of the via, while leaving a second portion of the sacrificial layer inside the via to maintain coverage over the SAM within the via.

5. The method of claim 4, further comprising removing the first portion of the SAM over the insulating layer, wherein prior to being removed, the first portion of the SAM is not covered by the second portion of the sacrificial layer.

6. The method of claim 5, further comprising removing the second portion of the sacrificial layer inside the via to expose the SAM within the via.

7. The method of claim 1, wherein, prior to removing the SAM at the sidewall of the via, the SAM at the sidewall of the via has a thickness that is less than the SAM at the bottom of the via.

8. A method of making a semiconductor device, the method comprising:

forming a first conductive layer over a substrate;

forming an insulating layer on the first conductive layer;

forming a via through the insulating layer to expose the first conductive layer;

forming a self-assembled monolayer (SAM) over a bottom of the via;

forming a barrier layer at a sidewall of the via;

removing the SAM over the bottom of the via; and

forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

9. The method of claim 8, further comprising forming the SAM at the sidewall of the via.

10. The method of claim 9, further comprising removing the SAM at the sidewall of the via, while leaving the SAM at the bottom of the via.

11. The method of claim 10, wherein, prior to removing the SAM at the sidewall of the via, a thickness of the SAM at the sidewall of the via is less than a thickness of the SAM at the bottom of the via.

12. The method of claim 8, further comprising, after forming the SAM at the sidewall of the via, and the bottom of the via, forming a sacrificial layer over the SAM.

13. The method of claim 12, wherein the sacrificial layer comprises an organic material.

14. The method of claim 8, further comprising forming the SAM over the insulating layer.

15. The method of claim 14, further comprising removing a first portion of the SAM over the insulating layer, while leaving a second portion of the SAM at the sidewall and the bottom of the via.

16. A method of making a semiconductor device, the method comprising:

forming a first conductive layer over a substrate;

forming an insulating layer on the first conductive layer;

forming a via through the insulating layer to expose the first conductive layer;

forming a barrier layer at a sidewall of the via, without forming the barrier layer at a bottom of the via; and

forming a second conductive layer over the barrier layer and the bottom of the via.

17. The method of claim 16, further comprising forming a self-assembled monolayer (SAM) over the bottom of the via prior to depositing the barrier layer.

18. The method of claim 17, further comprising removing the SAM from the bottom of the via prior to depositing the second conductive layer.

19. The method of claim 18, further comprising:

forming the SAM at the sidewall of the via and the bottom of the via prior to forming the barrier layer; and

removing the SAM at the sidewall of the via, wherein, prior to removing the SAM at the sidewall of the via, a thickness of the SAM at the sidewall of the via is less than a thickness of the SAM at the bottom of the via.

20. A semiconductor device comprising:

a first conductive layer over a substrate;

an insulating material on the first conductive layer, wherein a via is formed through the insulating material;

a barrier layer over the insulating material and within the via at a sidewall of the via without being at a bottom portion of the via; and

a second conductive layer over the barrier layer and within the via, wherein the barrier layer is not between the first conductive layer and the second conductive layer at the bottom portion of the via.