HIGH BREAKDOWN VOLTAGE INTER-METAL DIELECTRIC LAYER

• US 20200135552A1
• Filed: 06/05/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liou, Joung-Wei, Lan, Chin Kun
• Granted Patent: US 11,769,692 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers

Abstract

The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

Claims

1. A method of forming a semiconductor structure, comprising:

depositing an etch stop layer (ESL) over a first dielectric layer, wherein the depositing comprises;

flowing a first precursor over the first dielectric layer;

purging at least a portion of the first precursor;

flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and

purging at least a portion of the second precursor;

depositing a second dielectric layer on the ESL layer; and

forming a via in the second dielectric layer and through the ESL layer.

2. The method of claim 1, wherein depositing the ESL layer comprises depositing aluminum oxide.

3. The method of claim 1, wherein the first precursor comprises trimethylaluminum (TMA).

4. The method of claim 1, wherein the second precursor comprises one of tert-butanol ((CH₃)₃COH), H₂O, ethylene glycol, or tert-amyl alcohol (TAA).

5. The method of claim 1, further comprising performing a plasma treatment process on the first dielectric layer before the flowing of the first precursor.

6. The method of claim 5, wherein performing the plasma treatment process comprises flowing NH₃ over the first dielectric layer at a temperature between about 150 degrees Celsius and about 400 degrees Celsius and at a chamber pressure between about 0.5 Torr and about 10 Torr.

7. The method of claim 1, further comprising performing a plasma treatment process on the sublayer of the ESL layer.

8. The method of claim 7, wherein performing the plasma treatment process comprises flowing NH₃ over the sublayer of the ESL layer.

9. The method of claim 7, wherein a temperature of the plasma treatment process is between about 150 degrees Celsius and about 400 degrees Celsius.

10. A method of forming a semiconductor structure, comprising:

forming a conductive structure in a first dielectric layer;

depositing a second dielectric layer over the first dielectric layer, wherein the depositing comprises;

flowing a first precursor over the first dielectric layer;

removing at least a portion of the first precursor;

flowing a second precursor over the first dielectric layer; and

removing at least a portion of the second precursor;

depositing a third dielectric layer on the second dielectric layer; and

forming a via in the third dielectric layer and through the second dielectric layer.

11. The method of claim 10, wherein depositing the second dielectric layer comprises depositing aluminum oxide.

12. The method of claim 10, wherein the first precursor comprises trimethylaluminum (TMA).

13. The method of claim 10, wherein the second precursor comprises one of tert-butanol ((CH₃)₃COH), H₂O, ethylene glycol, or tert-amyl alcohol (TAA).

14. The method of claim 10, further comprising performing a plasma treatment process on the first dielectric layer before flowing of the first precursor.

15. The method of claim 10, wherein forming a conductive structure comprises depositing cobalt.

16. The method of claim 15, further comprising depositing copper in the via.

17. A semiconductor interconnect structure, comprising:

a first conductive structure in a first dielectric layer;

an aluminum oxide layer over the first dielectric layer, wherein a dielectric constant of the aluminum oxide layer is between about 7 and about 8.5;

a second dielectric layer on the aluminum oxide layer;

a second conductive structure in the second dielectric layer and through the aluminum oxide layer, wherein the first and second conductive structures are connected.

18. The semiconductor interconnect structure of claim 17, wherein the aluminum oxide layer comprises atomic concentrations of:

(i) aluminum between about 30%, and about 45%;

(ii) oxygen between about 55% and about 70%; and

(iii) hydrogen between about 0.5% and about 3%.

19. The semiconductor interconnect structure of claim 17, wherein a thickness of the aluminum oxide layer is between about 5 angstroms and about 50 angstroms.

20. The semiconductor interconnect structure of claim 17, wherein an atomic ratio of oxygen to aluminum of the aluminum oxide layer is between about 1.2 and about 2.3.