METHOD FOR FORMING AN INTERCONNECT STRUCTURE

• US 20200135555A1
• Filed: 06/12/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIU, Wen-Kuei
• Granted Patent: US 11,069,570 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288

Abstract

The present disclosure relates to a method of forming an interconnect structure. The method can include providing a semiconductor substrate; depositing a photoresist and a BARC layer on the semiconductor substrate; forming an opening in the photoresist and the BARC layer and a portion of the semiconductor substrate; depositing a conductive material to fill the opening; and planarizing the conductive material and the semiconductor substrate.

Claims

1. A method of forming an interconnect structure, comprising:

providing a semiconductor substrate;

depositing a photoresist and a bottom anti-reflective coating (BARC) layer on the semiconductor substrate;

forming an opening in the photoresist and the BARC layer and a portion of the semiconductor substrate;

depositing a conductive material to fill the opening; and

planarizing the conductive material and the semiconductor substrate.

2. The method of claim 1, wherein depositing the photoresist and the BARC layer on the semiconductor substrate comprises depositing the photoresist and the BARC as a single layer.

3. The method of claim 1, wherein depositing the photoresist and the BARC layer on the semiconductor substrate comprises depositing the photoresist and the BARC as two separate layers.

4. The method of claim 1, further comprising baking the photoresist and BARC layer at a temperature between about 100°

C. and about 1000°

C.

5. The method of claim 1, further comprising depositing a barrier layer on the photoresist and the BARC layer and in the opening prior to depositing the conductive material.

6. The method of claim 5, further comprising depositing a seed layer on the barrier layer prior to depositing the conductive material.

7. The method of claim 1, wherein planarizing the conductive material and the semiconductor substrate comprises removing the photoresist and the BARC layer, performing a chemical mechanical polishing (CMP) process, or a combination thereof.

8. The method of claim 7, wherein removing the photoresist and the BARC layer comprises performing a plasma etching process.

9. The method of claim 8, wherein the plasma etching process comprises an etching gas selected from oxygen, nitrogen, hydrogen, or a combination thereof.

10. The method of claim 9, wherein the etching gas flows at a rate between about 1 ml/min and about 2000 ml/min.

11. The method of claim 8, wherein performing the plasma etching process comprises performing the plasma etch process at a temperature between about 280°

C. and about 1000°

C.

12. A method, comprising:

depositing a photoresist and a bottom anti-reflective coating (BARC) layer on a semiconductor substrate;

forming an opening in the photoresist and the BARC layer and the semiconductor substrate;

depositing, via an electroplating process, a conductive material in the opening; and

planarizing the semiconductor substrate.

13. The method of claim 12, wherein depositing the conductive material comprises performing the electroplating process at a temperature between about 0°

C. and about 600°

C.

14. The method of claim 12, wherein depositing the conductive material comprises performing the electroplating process with a power supply of direct current, alternating current, or a combination thereof and with a power between about 1 watt and about 10000 watts.

15. The method of claim 12, wherein depositing the conductive material comprises performing the electroplating process with a current density between about 0.01 A/m and about 10000 A/m and a voltage between about 0.01 volt and about 10000 volts.

16. A method, comprising:

depositing a photoresist and a bottom anti-reflective coating (BARC) layer on a substrate;

depositing a barrier layer and a seed layer on the substrate;

forming an interconnect structure in a portion of the substrate by depositing a conductive material to fill an opening structure on the substrate; and

performing a chemical mechanical polishing (CMP) process to planarize the interconnect structure and the substrate.

17. The method of claim 16, wherein depositing the conductive material to fill the opening structure on the substrate comprises performing an electroplating process.

18. The method of claim 16, wherein performing the CMP process comprises:

securing the substrate onto a substrate carrier;

pressing the substrate against a polishing pad;

dispensing a CMP slurry onto the polishing pad; and

rotating the substrate carrier or the polishing pad.

19. The method of claim 18, wherein dispensing the CMP slurry onto the polishing pad comprises dispensing a first reactant, an abrasive, a first surfactant, a solvent, or a combination thereof, with a flow rate between about 1 ml/min and about 1000 ml/min.

20. The method of claim 18, wherein the CMP slurry comprises hydrogen peroxide, hydroxylamine, periodic acid, ammonium persulfate, other periodates, iodates, peroxomono, sulfates, peroxymonosulfuric acid, perborates, malonamide, nitric acid, colloidal silica, fumed silica, aluminum oxide, cerium oxide, carbon particles, titanium dioxide, polycrystalline diamond, polymethacrylate, polymethacryclic, or a combination thereof.