CONTROLLING GRAIN BOUNDARIES IN HIGH ASPECT-RATIO CONDUCTIVE REGIONS
First Claim
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1. A semiconductor structure comprising:
- a first conductive material formed in a first trench, wherein the first conductive material includes a first grain boundary level;
a second conductive material formed in a second trench, wherein the second conductive material includes a second grain boundary level;
a third conductive material formed in a third trench, wherein the third conductive material includes a third grain boundary level;
a first liner layer formed over the first conductive material and the second conductive material; and
a second liner layer formed over the first liner layer and the third conductive material.
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Abstract
Methods for forming high aspect-ratio conductive regions of a metallization network with reduced grain boundaries are described. Aspects of the invention include forming a trench in a dielectric material on the substrate. A conductive material is formed in the trench, wherein the conductive material includes a first grain boundary level. Portions of the dielectric material are removed to expose sidewalls of the conductive material. The conductive material is annealed to reduce the first grain boundary level.
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7 Claims
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1. A semiconductor structure comprising:
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a first conductive material formed in a first trench, wherein the first conductive material includes a first grain boundary level; a second conductive material formed in a second trench, wherein the second conductive material includes a second grain boundary level; a third conductive material formed in a third trench, wherein the third conductive material includes a third grain boundary level; a first liner layer formed over the first conductive material and the second conductive material; and a second liner layer formed over the first liner layer and the third conductive material. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification