CONTROLLING GRAIN BOUNDARIES IN HIGH ASPECT-RATIO CONDUCTIVE REGIONS

• US 20200135556A1
• Filed: 01/02/2020
• Published: 04/30/2020
• Est. Priority Date: 06/08/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Murray, Conal, Yang, Chih-Chao
• Granted Patent: US 10,903,115 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

Methods for forming high aspect-ratio conductive regions of a metallization network with reduced grain boundaries are described. Aspects of the invention include forming a trench in a dielectric material on the substrate. A conductive material is formed in the trench, wherein the conductive material includes a first grain boundary level. Portions of the dielectric material are removed to expose sidewalls of the conductive material. The conductive material is annealed to reduce the first grain boundary level.

Claims

1. A semiconductor structure comprising:

a first conductive material formed in a first trench, wherein the first conductive material includes a first grain boundary level;

a second conductive material formed in a second trench, wherein the second conductive material includes a second grain boundary level;

a third conductive material formed in a third trench, wherein the third conductive material includes a third grain boundary level;

a first liner layer formed over the first conductive material and the second conductive material; and

a second liner layer formed over the first liner layer and the third conductive material.

2. The semiconductor structure of claim 1, wherein the first trench comprises an aspect ratio greater than or equal to about 2.5.

3. The semiconductor structure of claim 1, wherein the second trench comprises an aspect ratio less than or equal to about 2.5.

4. The semiconductor structure of claim 1 further comprising a protective layer on the exposed sidewalls of the first conductive material.

5. The semiconductor structure of claim 4, wherein the protective layer comprises hydrogen silsesquixane.

6. The semiconductor structure of claim 1, wherein the first trench and the second trench each comprise an aspect ratio less than about 2.5.

7. The semiconductor structure of claim 1 further comprising:

a second dielectric material over the first liner layer; and

one or more airgaps in the second dielectric material between the first conductive material and the second conductive material.