Selective Deposition for Integrated Circuit Interconnect Structures

• US 20200135557A1
• Filed: 09/20/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Hsin-Yen, Lee, Shao-Kuan, Lee, Cheng-Chin, Chen, Hai-Ching, Shue, Shau-Lin
• Granted Patent: US 11,335,596 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53295 Stacked insulating layers

Abstract

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Claims

1. A method of forming an integrated circuit device comprising:

receiving a workpiece that includes a substrate and an interconnect structure disposed on the substrate, wherein the interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer;

selectively forming a blocking layer on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer;

selectively forming an alignment feature on the first inter-level dielectric layer without forming the alignment feature on the blocking layer;

removing the blocking layer from the first conductive feature;

forming a second inter-level dielectric layer on the alignment feature and on the first conductive feature;

patterning the second inter-level dielectric layer to define a recess for a second conductive feature; and

forming the second conductive feature within the recess such that the second conductive feature extends to the first conductive feature.

2. The method of claim 1 further comprising performing a surface treatment on a top surface of the first conductive feature, wherein the surface treatment promotes the forming of the blocking layer on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer.

3. The method of claim 2, wherein the surface treatment applies a reagent from a group consisting of:

an oxidizing agent and a reducing agent to the top surface of the first conductive feature.

4. The method of claim 2, wherein the surface treatment applies a reagent from a group consisting of:

NH₃, N₂, H₂, O₂, and H₂O to the top surface of the first conductive feature.

5. The method of claim 1, wherein the blocking layer includes a material with a head group from a group consisting of:

phosphorus, sulfur, and silicon that is configured to bond to a top surface of the first conductive feature.

6. The method of claim 1, wherein the forming of the alignment feature includes:

forming a catalyst on the first inter-level dielectric layer, wherein the blocking layer inhibits formation of the catalyst on the first conductive feature; and

forming the alignment feature on the catalyst.

7. The method of claim 6, wherein the catalyst includes a material from a group consisting of:

a metal and a metal oxide.

8. The method of claim 1, wherein the second conductive feature includes a via that includes a first portion that extends to and physically couples to the first conductive feature and a second portion that extends to the alignment feature.

9. The method of claim 8, wherein the interconnect structure includes a third conductive feature disposed within the first inter-level dielectric layer such that the alignment feature is disposed between and physically separates the second portion of the via from the third conductive feature.

10. The method of claim 1 further comprising forming an etch stop layer disposed on a top surface of the first conductive feature and on a top surface and side surfaces of the alignment feature, wherein the second inter-level dielectric layer is formed on the etch stop layer.

11. A method comprising:

receiving a workpiece that includes an interconnect structure, wherein the interconnect structure includes a first conductive line disposed within a first inter-level dielectric layer, and wherein the first conductive line includes a first liner, a first conductive fill disposed on the first liner, and a cap disposed on the first liner and on the first conductive fill;

performing a surface treatment on the cap;

forming a blocking layer on the cap without forming the blocking layer on the first inter-level dielectric layer, wherein the surface treatment is configured to promote bonding between the cap and the blocking layer;

forming a dielectric layer on the first inter-level dielectric layer and alongside the blocking layer;

removing the blocking layer to expose the cap of the first conductive line;

forming a second inter-level dielectric layer on the first conductive line and on the dielectric layer; and

forming a via in the second inter-level dielectric layer that couples to the first conductive line.

12. The method of claim 11, wherein a first portion of the via couples to the first conductive line and a second portion of the via couples to a top surface of the dielectric layer.

13. The method of claim 11, wherein the forming of the via includes forming a second conductive line on the via such that the via electrically couples the second conductive line to the first conductive line.

14. The method of claim 11, wherein the surface treatment applies a reagent from a group consisting of:

an oxidizing agent and a reducing agent to a top surface of the cap.

15. The method of claim 11, wherein the forming of the dielectric layer includes:

forming a catalyst on the first inter-level dielectric layer, wherein the blocking layer inhibits formation of the catalyst on the first conductive line; and

forming the dielectric layer on the catalyst.

16. The method of claim 15, wherein the blocking layer includes a material with a head group from a group consisting of:

phosphorus, sulfur, and silicon and a tail group configured to inhibit the forming of the catalyst on the blocking layer.

17. An integrated circuit device comprising:

a first conductive feature;

a first inter-level dielectric layer disposed alongside the first conductive feature;

an alignment feature disposed on the first inter-level dielectric layer;

a second conductive feature disposed on the first conductive feature and the alignment feature; and

a second inter-level dielectric layer disposed alongside the second conductive feature.

18. The integrated circuit device of claim 17, wherein the second conductive feature physically couples to a top surface of the first conductive feature and a top surface of the alignment feature.

19. The integrated circuit device of claim 17 further comprising a third conductive feature disposed alongside the first inter-level dielectric layer, wherein the alignment feature is disposed between the second conductive feature and the third conductive feature.

20. The integrated circuit device of claim 17 further comprising a catalyst disposed between the first inter-level dielectric layer and the alignment feature, wherein the catalyst includes a material from a group consisting of a metal and a metal oxide.