TRANSISTOR WITH IMPROVED SELF-ALIGNED CONTACT

• US 20200135561A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Bi, Zhenxing, Li, Juntao, Kong, Dexin
• Granted Patent: US 10,998,229 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors

Abstract

Systems, methods, and devices facilitating a transistor with an improved self-aligned contact are provided. In one example, a method comprises depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.

Claims

1. A semiconductor device, comprising:

a substrate;

a contact cap on a gate surface of the semiconductor device, wherein the contact cap extends from the gate surface to a first distance from the substrate of the semiconductor device;

a substrate contact on a non-gate surface of the semiconductor device, wherein the substrate contact extends from the substrate of the semiconductor device to a second distance from the substrate of the semiconductor device that is larger than the first distance; and

a second (CA) contact on the substrate contact, wherein the CA contact envelops at least a portion of the substrate contact.

2. The semiconductor device of claim 1, wherein the gate surface comprises a metal gate surface and at least one spacer surface.

3. The semiconductor device of claim 2, wherein the metal gate surface extends further from the substrate of the semiconductor device than the at least one spacer surface.

4. The semiconductor device of claim 1, further comprising:

a sacrificial cap layer formed onto the contact cap that extends to the second distance from the substrate of the semiconductor device.

5. The semiconductor device of claim 4, wherein the contact cap has a first etch sensitivity to an inter-layer dielectric, and wherein the sacrificial cap layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.

6. The semiconductor device of claim 4, wherein the sacrificial cap layer comprises a material, and wherein one or more surfaces of the substrate contact are lined with the material.

7. The semiconductor device of claim 1, further comprising:

an inter-level dielectric on at least a portion of the contact cap, the inter-level dielectric comprising a trench that defines an area of the CA contact.

8. The semiconductor device of claim 7, wherein the trench is formed into the inter-level dielectric at the area of the CA contact by reactive-ion etching.

9. A method, comprising:

depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and

depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.

10. The method of claim 9, wherein the first gate region, the second gate region, and the substrate contact region extend from a surface of a substrate of the semiconductor device to a first distance from the substrate, and wherein the method further comprises:

recessing the first gate region and the second gate region from the first distance from the substrate to a second distance from the substrate, wherein the second distance is less than the first distance.

11. The method of claim 10, wherein the depositing the dielectric layer comprises:

depositing the dielectric layer onto the first gate region and the second gate region such that the dielectric layer extends from the second distance from the substrate to the first distance from the substrate.

12. The method of claim 11, wherein the depositing the sacrificial layer comprises:

recessing the dielectric layer from the first distance from the substrate to a third distance from the substrate, wherein the third distance is less than the first distance and greater than the second distance; and

depositing the sacrificial layer onto the dielectric layer such that the sacrificial layer extends from the third distance from the substrate to the first distance from the substrate.

13. The method of claim 10, further comprising:

removing the substrate contact region by etching, resulting in an etched substrate contact region;

applying a liner to one or more surfaces of the etched substrate contact region; and

filling the etched substrate contact region such that the etched substrate contact region extends from the substrate of the semiconductor device to the first distance from the substrate, resulting in a filled substrate contact region.

14. The method of claim 13, further comprising:

removing the sacrificial layer, resulting in the filled substrate contact region extending further from the substrate of the semiconductor device than the dielectric layer.

15. The method of claim 14, further comprising:

forming a second (CA) contact onto the filled substrate contact region, wherein the CA contact envelops a portion of the filled substrate contact region that extends further from the substrate of the semiconductor device than the dielectric layer.

16. A semiconductor device comprising:

a substrate;

a gate on the substrate that extends from the substrate to a first distance from the substrate;

a spacer positioned adjacent to the gate on the substrate, the spacer extending from the substrate to a second distance from the substrate that is less than the first distance; and

a contact cap on the gate and the spacer, the contact cap extending from the gate and the spacer to a third distance from the substrate that is greater than the first distance and the second distance.

17. The semiconductor device of claim 16, wherein the contact cap comprises silicon nitride.

18. The semiconductor device of claim 16, further comprising:

a sacrificial cap layer on the contact cap.

19. The semiconductor device of claim 18, further comprising:

an inter-layer dielectric on the substrate, wherein the contact cap has a first etch sensitivity to the inter-layer dielectric, and wherein the sacrificial cap layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.

20. The semiconductor device of claim 18, wherein the sacrificial cap layer comprises titanium nitride.