SEMICONDUCTOR DEVICE WITH SELF-ALIGNED VIAS

• US 20200135562A1
• Filed: 02/13/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chien-Han, Chiu, Chien-Chih, Liang, Ming-Chung
• Granted Patent: US 11,502,001 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a conductive line over a substrate;

forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, wherein a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface;

forming a second dielectric layer over the ESL;

forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL;

removing the first portion of the ESL to expose the conductive line; and

filling the opening with an electrically conductive material to form a via.

2. The method of claim 1, wherein forming the conductive line comprising forming the conductive line in the first dielectric layer such that the conductive line and the first dielectric layer have a same level upper surface, wherein forming the etch stop layer comprises:

recessing the upper surface of the conductive line below the upper surface of the first dielectric layer; and

conformally forming the ESL over the upper surface of the first dielectric layer and over the recessed upper surface of the conductive line.

3. The method of claim 2, wherein recessing the upper surface of the conductive line comprises performing a wet etch that is selective to the conductive line.

4. The method of claim 3, wherein the conductive line is a copper line, and wherein the wet etch is performed using ammonium hydroxide.

5. The method of claim 2, wherein conformally forming the ESL comprises conformally forming a layer comprising metal oxide over the upper surface of the first dielectric layer and over the recessed upper surface of the conductive line, wherein the method further comprises conformally forming a layer comprising a dielectric material over the ESL before forming the second dielectric layer.

6. The method of claim 2, wherein filling the opening comprises:

forming a barrier layer lining a bottom and sidewalls of the opening; and

filling the opening with a metal material.

7. The method of claim 6, wherein the barrier layer covers a first portion of the upper surface of the conductive line, wherein the ESL covers a second portion of the upper surface of the conductive line.

8. The method of claim 1, wherein forming the conductive line comprising forming the conductive line in a third dielectric layer such that the conductive line and the third dielectric layer have a same level upper surface distal the substrate, wherein forming the etch stop layer comprises:

selectively forming the first dielectric layer over the third dielectric layer, the first dielectric layer exposing the upper surface of the conductive line; and

conformally forming the ESL over the upper surface of the first dielectric layer and over the upper surface of the conductive line.

9. The method of claim 8, wherein selectively forming the first dielectric layer comprises performing a deposition process using a first precursor comprising silicon and a second precursor comprising oxygen.

10. The method of claim 1, wherein a distance between the first lower surface of the ESL and the second lower surface of the ESL is between about 30 angstroms and about 50 angstroms.

11. A method of forming a semiconductor device, the method comprising

forming a conductive line in a first dielectric layer over a substrate, an upper surface of the conductive line being exposed at an upper surface of the first dielectric layer;

selectively forming a second dielectric layer on the upper surface of the first dielectric layer, an upper surface of the second dielectric layer extending further from the substrate than the upper surface of the conductive line;

forming a third dielectric layer over the second dielectric layer and the conductive line;

forming an opening in the third dielectric layer, the opening exposing a first portion of the upper surface of the conducive line and a second portion of the upper surface of the second dielectric layer; and

forming a via in the opening, the via being electrically coupled to the conductive line, a lower surface of the via extending along the first portion of the upper surface of the conductive line and the second portion of the upper surface of the second dielectric layer.

12. The method of claim 11, wherein the upper surface of the conductive line is formed to be level with the upper surface of the first dielectric layer.

13. The method of claim 11, wherein the second dielectric layer comprises silicon oxide, wherein selectively forming the second dielectric layer comprises selectively forming the second dielectric layer using a first precursor comprising silicon and a second precursor comprising oxygen.

14. The method of claim 11, wherein the upper surface of the second dielectric layer extends further from the substrate than the upper surface of the conductive line by a distance between about 30 angstroms and about 50 angstroms.

15. The method of claim 11, further comprising, before forming the third dielectric layer, forming a conformal etch stop layer over the upper surface of the conductive line and over the upper surface of the second dielectric layer.

16. The method of claim 15, wherein forming the opening in the third dielectric layer comprises:

performing a dry etch process to form a first opening in the third dielectric layer, the first opening exposing a portion of the conformal etch stop layer; and

performing a wet etch process to remove the exposed portion of the conformal etch stop layer.

17. A semiconductor device comprising:

a first dielectric layer over a substrate;

a conductive line in the first dielectric layer;

a second dielectric layer over the first dielectric layer and the conductive line; and

a via in the second dielectric layer and electrically coupled to the conductive line, wherein the via has opposing sidewalls and a bottom surface between the opposing sidewalls, wherein a first portion of the bottom surface of the via extends along an upper surface of the conductive line, and a second portion of the bottom surface of the via extends further from the substrate than the first portion.

18. The semiconductor device of claim 17, wherein an upper surface of the conductive line distal the substrate is closer to the substrate than an upper surface of the first dielectric layer distal the substrate.

19. The semiconductor device of claim 17, further comprising a third dielectric layer between the first dielectric layer and the second dielectric layer, wherein the second portion of the bottom surface of the via extends along an upper surface of the third dielectric layer distal the substrate.

20. The semiconductor device of claim 19, further comprising an etch stop layer between the third dielectric layer and the second dielectric layer.