GATE CUT CRITICAL DIMENSION SHRINK AND ACTIVE GATE DEFECT HEALING USING SELECTIVE DEPOSITION

• US 20200135575A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Greene, Andrew, Bergendahl, Marc, De Silva, Ekmini A., Joseph Varghese, Alex, MIGNOT, Yann, Shoudy, Matthew T., MUTHINTI, GANGADHARA RAJA, LEA, DALLAS
• Granted Patent: US 10,923,401 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a sacrificial gate over a shallow trench isolation region;

removing a portion of the sacrificial gate to expose a surface of the shallow trench isolation region;

depositing a semiconductor material on exposed sidewalls of the sacrificial gate; and

forming a gate cut dielectric on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

2. The method of claim 1, wherein the sacrificial gate comprises amorphous silicon or polysilicon.

3. The method of claim 2, wherein depositing the semiconductor material comprises a selective silicon on silicon deposition.

4. The method of claim 1 further comprising removing a remaining portion of the sacrificial gate to expose portions of the shallow trench isolation regions that are not covered by the gate cut dielectric.

5. The method of claim 1 further comprising:

forming a first conductive gate over a first portion of the shallow trench isolation region that is not covered by the gate cut dielectric; and

forming a second conductive gate over a second portion of the shallow trench isolation region that is not covered by the gate cut dielectric.

6. The method of claim 5, wherein a thickness of the gate cut dielectric defines a gate-to-gate spacing between the first conductive gate and the second conductive gate.

7. The method of claim 6, wherein the thickness of the gate cut dielectric is less than about 15 nm.

8. The method of claim 1, wherein the gate cut dielectric comprises SiN, SiON, SiC, SiOCN, or SiBCN.

9. The method of claim 1, wherein forming the sacrificial gate further comprises:

depositing a bulk sacrificial material over the shallow trench isolation; and

patterning the bulk sacrificial material to define the sacrificial gate.

10. The method of claim 9 further comprising forming a spacer on a sidewall of the sacrificial gate.

11. A method for forming a semiconductor device, the method comprising:

forming a first sacrificial gate in a gate cut region of a shallow trench isolation region;

forming a second sacrificial gate in an active gate region of the shallow trench isolation region;

removing a portion of the first sacrificial gate and a portion of the second sacrificial gate to expose a surface of the shallow trench isolation region;

depositing a semiconductor material on an exposed sidewall of the first sacrificial gate and on an exposed sidewall of the second sacrificial gate, the semiconductor material on the exposed sidewall of the second sacrificial gate completely covering the shallow trench isolation region; and

forming a gate cut dielectric on a portion of the shallow trench isolation region between sidewalls of the semiconductor material on the first sacrificial gate.

12. The method of claim 11, wherein the first sacrificial gate and the second sacrificial gate comprise amorphous silicon or polysilicon.

13. The method of claim 12, wherein depositing the semiconductor material comprises a selective silicon on silicon deposition.

14. The method of claim 11 further comprising removing the first sacrificial gate and the second sacrificial gate to expose portions of the shallow trench isolation region that are not covered by the gate cut dielectric.

15. The method of claim 11, further comprising:

forming a first conductive gate over a first portion of the shallow trench isolation region in the gate cut region that is not covered by the gate cut dielectric;

forming a second conductive gate over a second portion of the shallow trench isolation region in the gate cut region that is not covered by the gate cut dielectric; and

forming a third conductive gate over a third portion of the shallow trench isolation region in the active gate region.

16. The method of claim 15, wherein a thickness of the gate cut dielectric defines a gate-to-gate spacing between the first conductive gate and the second conductive gate.

17. The method of claim 16, wherein the thickness of the gate cut dielectric is less than about 15 nm.

18. The method of claim 11, wherein the gate cut dielectric comprises SiN, SiON, SiC, SiOCN, or SiBCN.

19. The method of claim 11, further comprising:

depositing a bulk sacrificial material over the shallow trench isolation region;

patterning the bulk sacrificial material to define the first sacrificial gate and the second sacrificial gate; and

forming a spacer on a sidewall of the second sacrificial gate.

20. The method of claim 19, wherein the semiconductor material fills a space between the spacer and the sidewall of the second sacrificial gate.