SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE

• US 20200135576A1
• Filed: 03/20/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHING, Kuo-Cheng, CHU, Lung-Kun, HUANG, Mao-Lin, HSU, Chung-Wei
• Granted Patent: US 11,024,545 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

Claims

1. A method for forming a semiconductor arrangement, comprising:

forming a first fin in a semiconductor layer;

forming a first gate dielectric layer comprising a first high-k material over the first fin;

forming a first sacrificial gate electrode over the first fin;

forming a dielectric layer adjacent the first sacrificial gate electrode and over the first fin;

removing the first sacrificial gate electrode to define a first gate cavity in the dielectric layer;

forming a second gate dielectric layer comprising a second dielectric material different than the first high-k material over the first gate dielectric layer in the first gate cavity; and

forming a first gate electrode in the first gate cavity over the second gate dielectric layer.

2. The method of claim 1, wherein forming the first gate dielectric layer comprises forming the first gate dielectric layer in the first gate cavity.

3. The method of claim 1, comprising forming a third gate dielectric layer over the first fin prior to forming the first sacrificial gate electrode.

4. The method of claim 3, wherein the second gate dielectric layer comprises silicon and oxygen and the third gate dielectric layer comprises silicon and oxygen.

5. The method of claim 1, wherein:

forming the first gate dielectric layer comprises forming the first gate dielectric layer prior to forming the first sacrificial gate electrode,

forming the first sacrificial gate electrode comprises forming the first sacrificial gate electrode over a first portion of the first gate dielectric layer, and

the method comprises removing a second portion of the first gate dielectric layer not covered by the first gate electrode prior to forming the dielectric layer.

6. The method of claim 1, comprising:

forming a second fin in the semiconductor layer;

forming a second sacrificial gate electrode over the second fin;

forming the dielectric layer adjacent the second sacrificial gate electrode and over the second fin;

removing the second sacrificial gate electrode to define a second gate cavity;

forming the first gate dielectric layer over the second fin in the second gate cavity;

forming the second gate dielectric layer over the first gate dielectric layer in the second gate cavity;

forming a mask in the first gate cavity prior to forming the first gate electrode;

removing the second gate dielectric layer in the second gate cavity;

removing the mask; and

forming a second gate electrode in the second gate cavity.

7. The method of claim 6, wherein forming the second gate electrode in the second gate cavity comprises forming the second gate electrode concurrently with forming the first gate electrode.

8. The method of claim 1, wherein:

the first fin comprises a first semiconductor material layer and a second semiconductor material layer over the first semiconductor material layer,

removing the first sacrificial gate electrode to define the first gate cavity in the dielectric layer exposes a portion of the first semiconductor material layer and a portion of the second semiconductor material layer, and

the method comprises removing one of the portion of the first semiconductor material layer or the portion of the second semiconductor material layer prior to forming the first gate dielectric layer.

9. The method of claim 8, wherein:

the first fin comprises a third semiconductor material layer under the first semiconductor material layer,

removing one of the portion of the first semiconductor material layer or the portion of the second semiconductor material layer prior to forming the first gate dielectric layer comprises removing the first semiconductor material layer to define an intermediate cavity between the second semiconductor material layer and the third semiconductor material layer,

forming the first gate dielectric layer comprises forming the first gate dielectric layer in the intermediate cavity,

forming the second gate dielectric layer comprises forming the second gate dielectric layer in the intermediate cavity, and

the method comprises removing a first portion of the second gate dielectric layer positioned in the first gate cavity, wherein a second portion of the second gate dielectric layer remains in the intermediate cavity.

10. A method for forming a semiconductor arrangement, comprising:

forming a first fin comprising a first semiconductor material layer, a second semiconductor material layer over the first semiconductor material layer, and a third semiconductor material layer over the second semiconductor material layer;

forming a first sacrificial gate electrode over the first fin;

forming a dielectric layer adjacent the first sacrificial gate electrode and over the first fin;

removing the first sacrificial gate electrode to define a first gate cavity in the dielectric layer and to expose a portion of the second semiconductor material layer;

removing the portion of the second semiconductor material layer to define a first intermediate cavity between the first semiconductor material layer and the third semiconductor material layer;

forming a first gate dielectric layer comprising a first high-k material in the first gate cavity and the first intermediate cavity;

forming a second gate dielectric layer comprising a second dielectric material different than the first high-k material over the first gate dielectric layer in the first gate cavity and the first intermediate cavity; and

forming a first gate electrode in the first gate cavity.

11. The method of claim 10, comprising:

forming a second fin comprising a fourth semiconductor material layer, a fifth semiconductor material layer over the fourth semiconductor material layer, wherein;

the first semiconductor material layer and the fourth semiconductor material layer comprise a first material, and

the second semiconductor material layer and the fifth semiconductor material layer comprise a second material different than the first material;

forming a second sacrificial gate electrode over the second fin;

forming the dielectric layer adjacent the second sacrificial gate electrode and over the second fin;

removing the second sacrificial gate electrode to define a second gate cavity in the dielectric layer and to expose a portion of the fourth semiconductor material layer;

forming a first mask in the second gate cavity, wherein removing the portion of the second semiconductor material layer comprises removing the portion of the second semiconductor material layer while the first mask is in the second gate cavity;

removing the first mask;

forming a second mask over the first gate cavity;

removing the portion of the fourth semiconductor material layer to define a second intermediate cavity while the second mask is in the first gate cavity; and

removing the second mask.

12. The method of claim 11, wherein the first semiconductor material layer and the third semiconductor material layer comprise the first material.

13. The method of claim 11, wherein:

the first material comprises a first silicon alloy with a first alloy concentration by atomic percentage, and

the second material comprises a second silicon alloy with a second alloy concentration by atomic percentage different than the first alloy concentration.

14. The method of claim 13, wherein the first silicon alloy comprises silicon and germanium.

15. The method of claim 11, comprising:

forming the first gate dielectric layer in the second gate cavity and the second intermediate cavity;

forming the second gate dielectric layer in the second gate cavity and the second intermediate cavity forming a third mask in the first gate cavity;

removing a first portion of the second gate dielectric layer positioned in the second gate cavity, wherein a second portion of the second gate dielectric layer remains in the second intermediate cavity;

removing the third mask, wherein forming the first gate electrode in the first gate cavity comprises forming the first gate electrode in the first gate cavity over the second gate dielectric layer; and

forming a second gate electrode in the second gate cavity over the first gate dielectric layer and over the second portion of the second gate dielectric layer.

16. The method of claim 10, comprising:

forming a third gate dielectric layer over the first semiconductor material layer and the third semiconductor material layer in the first gate cavity prior to forming the first gate dielectric layer.

17. A semiconductor arrangement, comprising:

a first fin; and

a first gate structure over the first fin, the first gate structure comprising;

a first gate dielectric layer comprising a first high-k material;

a second gate dielectric layer comprising a second material different than the first high-k material over the first gate dielectric layer; and

a first gate electrode over the second gate dielectric layer.

18. The semiconductor arrangement of claim 17, comprising a third gate dielectric layer over the first fin and under the first gate dielectric layer.

19. The semiconductor arrangement of claim 17, wherein:

the first fin comprises a first semiconductor material layer and a second semiconductor material layer, and

the first gate dielectric layer and the second gate dielectric layer are positioned between the first semiconductor material layer and the second semiconductor material layer.

20. The semiconductor arrangement of claim 19, wherein the first gate electrode directly contacts the first gate dielectric layer and directly contacts the second gate dielectric layer.