METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

• US 20200135577A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 09/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YEH, Ling-Yen, DIAZ, Carlos H., TSAI, Wilman
• Granted Patent: US 10,872,822 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a dielectric layer is formed over a channel layer in the MOSFET region and the NCFET region. A first metallic layer is formed over the dielectric layer in the MOSFET region and the NCFET region. After the first metallic layer is formed, an annealing operation is performed only in the NCFET region. After the annealing operation, the first metallic layer is removed from the MOSFET region and the NCFET region. The annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region with an energy beam.

Claims

1. A method of manufacturing a negative capacitance structure, the method comprising:

forming sidewall spacers at opposite ends of a gate region on top of a fin;

forming a dielectric layer over the fin in the gate region between the sidewall spacers and on the sidewall spacers;

forming a first metallic layer over the dielectric layer;

forming a cap layer over the first metallic layer;

after the cap layer is formed, performing an annealing operation; and

after the annealing operation, removing the cap layer and the first metallic layer; and

wherein the annealing operation includes irradiating the cap layer, the first metallic layer, and the dielectric layer in the gate region between the sidewall spacers and on upper parts of the sidewall spacers with an energy beam, and

after the annealing operation, the dielectric layer in the gate region between the sidewall spacers and on the upper parts of the sidewall spacers becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

2. The method of claim 1, wherein the dielectric layer includes one selected from the group consisting of HfO₂, ZrO₂ and SrTiO₃.

3. The method of claim 2, wherein the sidewall spacers include one or more layers comprising silicon oxide, silicon nitride, or silicon oxynitride.

4. The method of claim 1, wherein:

the dielectric layer includes HfO₂, and

the first metallic layer includes one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd, Mg and Sr.

5. The method of claim 1, wherein the energy beam heats the first metallic layer and the dielectric layer to a temperature in a range from 600°

C. to 1000°

C.

6. The method of claim 1, further comprising, after the annealing operation, removing the first metallic layer.

7. The method of claim 1, wherein the ferroelectric dielectric layer has a U-shape.

8. The method of claim 1, wherein the cap layer includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

9. The method of claim 1, further comprising, after the removing the cap layer and the first metallic layer, forming one or more second metallic layers over the dielectric layer.

10. The method of claim 1, wherein the energy beam includes one selected from the group consisting of an electron beam, an ion beam, a molecular beam, a laser light beam, and a neutral beam.

11. A method of manufacturing a circuit including a metal-oxide-semiconductor field effect transistor (MOSFET) disposed in a MOSFET region and a negative capacitance field effect transistor (NCFET) disposed in a NCFET region, the method comprising:

forming sidewall spacers at opposite ends of gate regions on top of fins in the MOSFET and NCFET regions;

forming a dielectric layer over the fins in the gate regions of the NCFET and MOSFET regions between the sidewall spacers and on the sidewall spacers;

forming a first metallic layer over the dielectric layer in the MOSFET region and the NCFET region;

after the first metallic layer is formed, performing an annealing operation only in the NCFET region; and

after the annealing operation, removing the first metallic layer from the MOSFET region and the NCFET region,

wherein the annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region between the sidewall spacers and on upper parts of the sidewall spacers in the NCFET region with an energy beam, and

after the annealing operation, in the NCFET region, the dielectric layer in the gate region between the sidewall spacers and on the upper parts of the sidewall spacers becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

12. The method of claim 11, wherein the dielectric layer includes amorphous HfO₂.

13. The method of claim 12, wherein the first metallic layer includes one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd, Mg and Sr.

14. The method of claim 12, wherein the energy beam includes one selected from the group consisting of an electron beam, an ion beam, a molecular beam, a laser light beam, and a neutral beam having an energy to heat the first metallic layer and the dielectric layer to a temperature in a range from 600°

C. to 1000°

C.

15. The method of claim 11, further comprising, before the annealing operation, forming a cap layer over the first metallic layer in the MOSFET region and the NCFET region.

16. The method of claim 15, wherein the cap layer includes silicon oxide.

17. The method of claim 15, further comprising, after the annealing operation, removing the cap layer and the first metallic layer from the MOSFET region and the NCFET region.

18. A method of manufacturing a circuit including a metal-oxide-semiconductor field effect transistor (MOSFET) disposed in a MOSFET region and a negative capacitance field effect transistor (NCFET) disposed in a NCFET region, the method comprising:

forming a first dummy gate structure over a first fin structure formed in the MOSFET region on a substrate and a second dummy gate structure over a second fin structure formed in the NCFET region on the substrate;

forming a first source/drain structure over the first fin structure on opposing sides of the first dummy gate structure and a second source/drain structure over the second fin structure on opposing sides of the second dummy gate structure;

forming an interlayer dielectric layer over the first and second source/drain structures;

removing the first dummy gate structure and the second dummy gate structure, thereby exposing a first channel region of the first fin structure and a second channel region of the first fin structure;

forming sidewall spacers at opposite ends of the first and second channel regions on top of the first and second fin structures in the MOSFET and NCFET regions;

forming a dielectric layer over the fin structures in the NCFET and MOSFET regions between the sidewall spacers, over the sidewalls of the first and second fin structures in the first and second channel regions from a top of the first and second channel regions to the substrate, and on the sidewall spacers;

forming a first metallic layer over the dielectric layer in the MOSFET region and the NCFET region;

after the first metallic layer is formed, performing an annealing operation only in the NCFET region; and

after the annealing operation, removing the first metallic layer from the MOSFET region and the NCFET region,

wherein the annealing operation includes irradiating, in the NCFET region, the first metallic layer and the dielectric layer between the sidewall spacers and the sidewalls of the second fin structure in the second channel region with an energy beam and irradiating the first metallic layer and the dielectric layer on the sidewall spacers of the NCFET region with the energy beam, and

after the annealing operation, in the NCFET region, the dielectric layer over the second fin structure, on the sidewalls of the second fin structure, and on the of the sidewall spacers of the NCFET region becomes a ferroelectric layer including an orthorhombic crystal phase.

19. The method of claim 18, further comprising forming one or more second metallic layers over the dielectric layer in the MOSFET region and over the ferroelectric layer in the NCFET region.

20. The method of claim 18, wherein:

the dielectric layer in the MOSFET region after the first metallic layer is removed includes amorphous HfO₂, and

the ferroelectric layer in the NCFET region includes HfO₂ doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd, Mg and Sr.