Semiconductor Device and Method

• US 20200135579A1
• Filed: 09/11/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Shih-Chieh, Wu, Pang-Chi, Chao, Kuo-Yi, Wang, Mei-Yun, Liao, Hsien-Huang, Hsieh, Tung-Heng, Young, Bao-Ru
• Granted Patent: US 10,957,604 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Claims

1. A method comprising:

forming a first fin extending from a substrate;

forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance;

forming a metal gate stack over the first fin and the second fin;

depositing a first inter-layer dielectric over the metal gate stack; and

forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance,

wherein the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

2. The method of claim 1, wherein the metal gate stack has multiple widths, and a portion of the metal gate stack with a narrowest width of the multiple widths is disposed over the first fin.

3. The method of claim 2, wherein the first predetermined threshold is in a range of 35 to 40 times the narrowest width of the metal gate stack.

4. The method of claim 2, wherein the second predetermined threshold is in a range of 10 to 13 times the narrowest width of the metal gate stack.

5. The method of claim 2, wherein the narrowest width of the metal gate stack is in a range of 6 nm to 300 nm.

6. The method of claim 1 further comprising:

depositing a second inter-layer dielectric around the metal gate stack, wherein after the second inter-layer dielectric is formed, a first portion of the metal gate stack comprises a void.

7. The method of claim 6, wherein the gate contact physically contacts a second portion of the metal gate stack, the first portion of the metal gate stack being distal the first fin, the second portion of the metal gate stack being proximate the first fin.

8. The method of claim 7, wherein the first portion of the metal gate stack and the second portion of the metal gate stack are laterally disposed between the first fin and the second fin.

9. A method comprising:

forming a first fin extending from a substrate;

forming a dummy gate stack over the first fin;

depositing a first inter-layer dielectric along the dummy gate stack;

replacing the dummy gate stack with a metal gate stack, an end of the metal gate stack being rounded, the metal gate stack comprising a void, the void being disposed a first distance from the rounded end of the metal gate stack;

forming a second inter-layer dielectric over the metal gate stack and the first inter-layer dielectric; and

forming a gate contact extending through the second inter-layer dielectric to physically contact a first portion of the metal gate stack, the first portion of the metal gate stack being disposed a second distance from the rounded end of the metal gate stack, the second distance being greater than the first distance.

10. The method of claim 9, wherein the first distance is in a range of 50 nm to 90 nm, and the second distance is in a range of 91 nm to 500 nm.

11. The method of claim 9, wherein the first fin has a first width, the gate contact has a second width, and the second distance is greater than a sum of half of the first width and half of the second width.

12. The method of claim 9, wherein the first fin is adjacent the rounded end of the metal gate stack.

13. The method of claim 9, wherein replacing the dummy gate stack with the metal gate stack comprises:

etching the dummy gate stack to form a recess having a rounded end; and

filling the recess with a metal, the void being formed during the filling.

14. A method comprising:

forming a first fin extending from a substrate;

forming a second fin extending from the substrate;

forming a metal line over the first fin and the second fin;

cutting the metal line along a first region to separate the metal line into a first metal gate stack and a second metal gate stack, the first metal gate stack being over the first fin, the second metal gate stack being over the second fin;

depositing a first inter-layer dielectric over the first metal gate stack and the second metal gate stack;

forming a first gate contact extending through the first inter-layer dielectric to physically contact the first metal gate stack, the first gate contact being disposed a first distance from the first region; and

forming a second gate contact extending through the first inter-layer dielectric to physically contact the second metal gate stack, the second gate contact being disposed the first distance from the first region.

15. The method of claim 14, wherein cutting the metal line comprises:

etching the metal line in the first region to form a first opening through the metal line; and

forming a dielectric material in the first opening.

16. The method of claim 15, wherein the first inter-layer dielectric is further deposited over the dielectric material.

17. The method of claim 15 further comprising:

forming gate spacers adjacent the metal line, the dielectric material extending between the gate spacers.

18. The method of claim 17 further comprising:

forming a second inter-layer dielectric around the gate spacers.

19. The method of claim 14, wherein the first fin and the first metal gate stack are part of a first transistor, and wherein the second fin and the second metal gate stack are part of a second transistor.

20. The method of claim 14, wherein ends of the first metal gate stack and the second metal gate stack are free from voids.