Dielectric Fins With Different Dielectric Constants and Sizes in Different Regions of a Semiconductor Device

• US 20200135580A1
• Filed: 09/20/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Min-Yann, Chen, Hua Feng, Liaw, Jhon Jhy
• Granted Patent: US 11,282,751 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Claims

1. A semiconductor device, comprising:

a first epi-layer and a second epi-layer each located in a first region of the semiconductor device;

a first dielectric fin located between the first epi-layer and the second epi-layer, wherein the first dielectric fin has a first dielectric constant;

a third epi-layer and a fourth epi-layer each located in a second region of the semiconductor device; and

a second dielectric fin located between the third epi-layer and the fourth epi-layer, wherein the second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

2. The semiconductor device of claim 1, wherein:

the first dielectric fin has a first height;

the second dielectric fin has a second height; and

the first height is greater than the second height.

3. The semiconductor device of claim 2, wherein:

the first epi-layer or the second epi-layer has a third height; and

the third height is greater than or equal to the first height.

4. The semiconductor device of claim 1, wherein:

an upper surface of the first dielectric fin is disposed above an outermost lateral protrusion of the first epi-layer and the second epi-layer; and

an upper surface of the second dielectric fin is disposed below an outermost lateral protrusion of the third epi-layer and the fourth epi-layer.

5. The semiconductor device of claim 1, wherein the second dielectric fin includes a greater number of dielectric materials than the first dielectric fin.

6. The semiconductor device of claim 5, wherein:

the first dielectric fin is comprised of a first type of dielectric material having a first dielectric constant;

the second dielectric fin is comprised of a second type of dielectric material having a second dielectric constant and a third type of dielectric material having a third dielectric constant;

the first dielectric constant is greater than the second dielectric constant; and

the second dielectric constant is greater than the third dielectric constant.

7. The semiconductor device of claim 6, wherein the third type of dielectric material is located over the second type of dielectric material in the second dielectric fin.

8. The semiconductor device of claim 6, wherein:

the first dielectric constant is greater than about 10;

the second dielectric constant is less than about 10 but greater than about 4; and

the third dielectric constant is less than about 5.

9. The semiconductor device of claim 1, the second dielectric fin is at least twice as wide as the first dielectric fin.

10. The semiconductor device of claim 1, wherein:

the first region includes a memory device region; and

the second region includes a logic device region.

11. The semiconductor device of claim 1, wherein:

the first region has a first pattern density;

the second region has a second pattern density; and

the first pattern density is greater than the second pattern density.

12. The semiconductor device of claim 11, wherein the first pattern density is at least twice as great as the second pattern density.

13. A semiconductor device, comprising:

a first source/drain and a second source/drain disposed in a memory device region of the semiconductor device;

a high-k fin structure disposed between the first source/drain and the second source/drain;

a third source/drain and a fourth source/drain disposed in a logic device region of the semiconductor device; and

a hybrid fin structure disposed between the third source/drain and the fourth source/drain;

wherein;

the first source/drain and the second source/drain are spaced apart by a first distance;

the third source/drain and the fourth source/drain are spaced apart by a second distance greater than the first distance;

the high-k fin structure has a greater dielectric constant than the hybrid fin structure;

an upper surface of the high-k fin structure is disposed above an upper surface of the hybrid fin structure; and

the hybrid fin structure comprises multiple types of different dielectric materials.

14. The semiconductor device of claim 13, wherein:

the upper surface of the high-k fin structure is disposed above an outermost lateral protrusion of the first source/drain and the second source/drain; and

the upper surface of the hybrid fin structure is disposed below an outermost lateral protrusion of the third source/drain and the fourth source/drain.

15. A method, comprising:

providing a semiconductor device that includes a plurality of device fin structures formed in a first region and a second region of the semiconductor device, wherein a first trench exists between the device fin structures in the first region, and wherein a second trench exists between the device fin structures in the second region;

partially filling the first trench with a first dielectric layer;

partially filling the second trench with a second dielectric layer, wherein the second dielectric layer has a lower dielectric constant than the first dielectric layer;

forming a third dielectric layer over the second dielectric layer, wherein the third dielectric layer has a lower dielectric constant than the second dielectric layer;

partially removing the third dielectric layer and the second dielectric layer such that the second trench is partially filled by remaining portions of the third dielectric layer and the second dielectric layer;

recessing the device fin structures; and

growing epi-layers over the recessed device fin structures, wherein the first dielectric layer separates a first subset of the device fin structures in the first region, and wherein the remaining portions of the third dielectric layer and the second dielectric layer separates a second subset of the device fin structures in the second region.

16. The method of claim 15, wherein:

the first region includes a memory device region and has a first pattern density;

the second region includes a logic device region and has a second pattern density; and

the first pattern density is greater than the second pattern density.

17. The method of claim 15, wherein the partially removing the third dielectric layer and the second dielectric layer is performed using a planarization process followed by an etch back process.

18. The method of claim 15, wherein:

the recessing the device fin structures is performed using an etching process having a first etching rate with respect to the first dielectric layer, a second etching rate with respect to the second dielectric layer or the third dielectric layer, and a third etching rate with respect to the device fin structures;

the first etching rate is less than the second etching rate; and

the second etching rate is less than the third etching rate.

19. The method of claim 18, wherein after the etching process and the growing the epi-layers are performed:

the first dielectric layer is shorter than the epi-layers; and

the remaining portions of the third dielectric layer and the second dielectric layer are shorter than the first dielectric layer.

20. The method of claim 15, further comprising, after the partially removing the third dielectric layer and the second dielectric but before the recessing the device fin structures:

forming a fourth dielectric layer over the remaining portions of the third dielectric layer and the second dielectric layer;

forming a fifth dielectric layer over the fourth dielectric layer, wherein the fifth dielectric layer has a lower dielectric constant than the fourth dielectric layer; and

performing a planarization process to the fifth dielectric layer and the fourth dielectric layer until the device fin structures are reached.