Method and Structure for FinFET Isolation

• US 20200135581A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Lin, Jr-Jung
• Granted Patent: US 10,867,865 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a substrate and a fin protruding from the substrate, the fin having a first fin segment and a second fin segment discontinued from the first fin segment. The semiconductor device further includes an isolation feature disposed between the first and second fin segments and a spacer feature disposed on sidewalls of an upper portion of the isolation feature and surrounding the isolation feature from a top view.

Claims

1. A semiconductor device, comprising:

a substrate;

a fin protruding from the substrate, the fin having a first fin segment and a second fin segment discontinued from the first fin segment;

an isolation feature disposed between the first and second fin segments; and

a spacer feature disposed on sidewalls of an upper portion of the isolation feature and surrounding the isolation feature from a top view.

2. The semiconductor device of claim 1, further comprising:

a first gate stack over the substrate and engaging the first fin segment; and

a second gate stack over the substrate and engaging the second fin segment.

3. The semiconductor device of claim 2, wherein a bottom surface of either the first gate stack or the second gate stack is above a bottom surface of the isolation feature.

4. The semiconductor device of claim 1, wherein a portion of the isolation feature is directly under the spacer feature.

5. The semiconductor device of claim 1, further comprising:

a dielectric material layer disposed between the isolation feature and each of the first and second fin segments.

6. The semiconductor device of claim 5, wherein a portion of the dielectric material layer is directly under the spacer feature.

7. The semiconductor device of claim 5, wherein a portion of the dielectric material layer is disposed between a bottom surface of the isolation feature and the substrate.

8. The semiconductor device of claim 5, wherein a thickness of the dielectric material layer is smaller than a thickness of the spacer feature.

9. The semiconductor device of claim 1, wherein the isolation feature is a first isolation feature, further comprising:

a second isolation feature disposed over and in physical contact with an end of the first fin segment, wherein the first fin segment is disposed between the first and second isolation features; and

a third isolation feature disposed over and in physical contact with an end of the second fin segment, wherein the second fin segment is disposed between the first and third isolation features.

10. The semiconductor device of claim 9, wherein the first, second, and third isolation features comprise a same material composition.

11. The semiconductor device of claim 9, wherein the first isolation feature comprises a material composition different from that of either the second isolation feature or the third isolation feature.

12. A semiconductor device, comprising:

a substrate;

a first dielectric layer over the substrate;

a fin protruding from the substrate and through the first dielectric layer, the fin having a first fin segment and a second fin segment discontinued from the first fin segment;

an isolation structure disposed between the first and second fin segments; and

a second dielectric layer disposed between a lower portion of the isolation structure and each of the first and second fin segments.

13. The semiconductor device of claim 12, wherein a portion of the second dielectric layer is disposed between a bottom surface of the isolation structure and the substrate.

14. The semiconductor device of claim 12, wherein a bottom surface of the isolation structure is below a top surface of the first dielectric layer.

15. The semiconductor device of claim 12, further comprising:

a spacer layer disposed on sidewalls of an upper portion of the isolation structure.

16. The semiconductor device of claim 15, wherein a portion of the fin is directly under the spacer layer.

17. The semiconductor device of claim 15, wherein a portion of the second dielectric layer is directly under the spacer layer.

18. A semiconductor device, comprising:

a substrate;

a fin protruding from the substrate and extending lengthwise along a first direction, the fin having a first fin segment and a second fin segment discontinued from the first fin segment; and

an isolation structure disposed between the first and second fin segments, wherein along the first direction an upper portion of the isolation structure is narrower than a lower portion of the isolation structure disposed below a top surface of the fin.

19. The semiconductor device of claim 18, wherein the isolation structure is a first isolation structure, further comprising:

a second isolation structure over and physically contacting an end of the first fin segment, wherein along the first direction an upper portion of the second isolation structure is wider than a lower portion of the second isolation structure disposed below the top surface of the fin; and

a third isolation structure over and physically contacting an end of the second fin segment, wherein along the first direction an upper portion of the third isolation structure is wider than a lower portion of the third isolation structure disposed below the top surface of the fin.

20. The semiconductor device of claim 18, further comprising:

a first gate stack over the substrate and engaging the first fin segment;

a second gate stack over the substrate and engaging the second fin segment; and

a spacer layer disposed on sidewalls of the first and second gate stacks and on sidewalls of the upper portion of the isolation structure.