SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20200135582A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 07/02/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Zhi-Cheng, Lee, Kai-Lin, Chen, Wei-Jen
• Granted Patent: US 11,011,430 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region;

forming a first fin-shaped structure on the first region;

forming a first gate structure and a second gate structure on the first fin-shaped structure;

using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and

forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

2. The method of claim 1, further comprising:

forming the first fin-shaped structure on the first region and a second fin-shaped structure on the second region;

removing part of the second fin-shaped structure to form a second trench;

forming a second dielectric layer in the second trench; and

planarizing the second dielectric layer to form a second SDB structure.

3. The method of claim 2, wherein the first fin-shaped structure and the second fin-shaped structure are disposed extending along a first direction and the first SDB structure and the second SDB structure are disposed extending along a second direction.

4. The method of claim 3, wherein the first direction is orthogonal to the second direction.

5. The method of claim 2, wherein the first SDB structure and the second SDB structure comprise different materials.

6. The method of claim 2, further comprising:

forming the first gate structure and the second gate structure on the first region and a third gate structure on the second SDB structure;

forming the patterned mask on the first region and the second region;

using the patterned mask to remove the first gate structure and part of the first fin-shaped structure to form the first trench;

forming the first dielectric layer in the first trench and around the second gate structure and the third gate structure;

performing a replacement metal gate (RMG) process to transform the second gate structure and the third gate structure into metal gates.

7. The method of claim 1, further comprising performing a flowable chemical vapor deposition (FCVD) process to form the first dielectric layer.

8. The method of claim 1, further comprising planarizing the first dielectric layer to form the first SDB structure and an interlayer dielectric (ILD) layer around the second gate structure.

9. The method of claim 1, wherein the first region comprises a NMOS region and the second region comprises a PMOS region.