FINFET DEVICES AND METHODS OF FORMING THE SAME

• US 20200135584A1
• Filed: 10/28/2018
• Published: 04/30/2020
• Est. Priority Date: 10/28/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chih-Hao, Huang, Jui-Chien, Ching, Kuo-Cheng, Lin, Chun-Hsiung, Wang, Pei-Hsun
• Granted Patent: US 10,847,426 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02614 Transformation of metal, e.g. oxidation, nitridation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin

Abstract

Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

Claims

1. A FinFET device, comprising:

a substrate having at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins, wherein the first fin comprises a first material layer and a second material layer over the first material layer, and an interface between the first material layer and the second material layer is uneven;

a first gate strip disposed across the first fin; and

a second gate strip disposed across the second fin.

2. The FinFET device of claim 1, wherein the second material layer has a tailing profile toward the isolation layer.

3. The FinFET device of claim 1, wherein the second material layer has two tailing portions in contact with the isolation layer.

4. The FinFET device of claim 1, wherein the first fin above the isolation layer is constituted by the second material layer.

5. The FinFET device of claim 1, wherein the first fin above the isolation layer is constituted by the second material layer surrounding the first material layer.

6. The FinFET device of claim 1, wherein the second material layer has a uniform germanium concentration within the first fin above the isolation layer.

7. The FinFET device of claim 1, wherein the second material layer has a gradient germanium concentration within the first fin above the isolation layer.

8. The FinFET device of claim 1, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.

9. The FinFET device of claim 1, wherein the first region is a P-type device region, and the second region is an N-type device region.

10. A method of forming a FinFET device, comprising:

providing a substrate having at least one first fin, the first fin comprising a first material;

performing a transforming process to the first fin to transform a portion of the first material into a second material, and an interface between the first material and the second material is uneven; and

forming a first gate strip across the first fin.

11. The method of claim 10, further comprising performing a trimming process to narrow a width of the first fin before the transforming process.

12. The method of claim 10, further comprising performing a trimming process to narrow a width of the first fin after the transforming process.

13. The method of claim 10, wherein the transforming process comprises:

forming a transforming layer comprising the second material on a surface of the first fin; and

performing an annealing process to drive the second material into the first fin.

14. The method of claim 13, wherein the substrate further has an isolation layer covering a lower portion of the first fin, and the second material of the transforming layer is further driven toward the isolation layer.

15. The method of claim 14, wherein the first material of the first fin above the isolation layer is completely transformed into the second material.

16. The method of claim 14, wherein the first material of the first fin above the isolation layer is partially transformed into the second material.

17. A method of forming a FinFET device, comprising:

providing a substrate having at least one first fin in a first region and at least one second fin in the second region, each of the first fin and the second fin comprises a first material;

forming a mask layer on a surface of the second fin in the second region;

forming a second material on a surface of the first fin in the first region;

driving the second material into the first fin;

removing the mask layer; and

forming a first gate strip and a second gate strip respectively across the first fin and the second fin.

18. The method of claim 17, further comprising performing a trimming process to narrow a width of the first fin after forming the mask layer and before forming the second material.

19. The method of claim 17, wherein the substrate further has an isolation layer covering lower portions of the first and second fins, and the second material is further driven toward the isolation layer.

20. The method of claim 19, wherein the second material has two tailing portions in contact with the isolation layer.