MASKLESS TOP SOURCE/DRAIN EPITAXIAL GROWTH ON VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR

• US 20200135585A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, ChoongHyun, Mochizuki, Shogo, Ok, Injo, Seo, Soon-Cheon
• Application Number:
  US16/173,754
• Publication Number:
  US 20200135585A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeO₂ layer on the top surface of the device and over the exposed SiGe portion of the first plurality of fins and the exposed portion of the second plurality of fins.

Claims

1. A method for fabricating a vertical transistor device, comprising:

forming a first plurality of fins in a first device region on a substrate, wherein the first plurality of fins comprises a first portion on the substrate and a second portion on the first portion, wherein the first portion is Si and the second portion is SiGe;

forming a second plurality of Si fins in a second device region on the substrate, wherein a length of the first plurality of fins is equal to a length of the second plurality of fins;

forming a plurality of metal gate layers on the substrate and on at least a portion of sidewalls of the first portion of the first plurality of fins and at least a portion of sidewalls of the second plurality of fins;

forming a spacer layer on the plurality of metal gate layers and in contact with the sidewalls of each of the first and second plurality of fins up to a top of the first portion of the first plurality of fins thereby exposing a remaining portion of the first plurality of fins and the second plurality of fins above a top surface of the spacer layer;

forming a dielectric layer on and up to the top surface of the spacer layer; and

forming a first GeO₂ layer on the top surface of the spacer layer and the dielectric layer and over the exposed portion of the first plurality of fins and the second plurality of fins.

2. The method according to claim 1, further comprising:

converting the GeO₂ layer on the exposed portion of the first plurality of fins to a first SiO₂ layer, and

removing a remaining amount of the first GeO₂ layer.

3. The method according to claim 2, wherein the converting step comprises heating the device in the presence of an inert gas such that the germanium in the first GeO₂ layer diffuses into the second portion of the first plurality of fins to provide an increased amount of germanium, and an amount of silicon in the second portion diffuses into and converts the first GeO₂ layer to the first SiO₂ layer.

4. The method according to claim 2, further comprising:

forming a plurality of top source/drain regions extending from the exposed portion of the second plurality of fins in the second device region; and

forming a common SiGe epitaxial layer to the plurality of top source/drain regions in the second device region.

5. The method according to claim 4, wherein the top source/drain regions are in a diamond shaped configuration.

6. The method according to claim 4, further comprising removing the first SiO₂ layer and the exposed portion of the second plurality of fins.

7. The method according to claim 6, further comprising depositing a second GeO₂ layer on the top surface of the spacer and the dielectric layers, an exposed top surface of the first section of the first plurality of fins and over the common SiGe epitaxial layer to the plurality of top source/drain regions in the second device region.

8. The method according to claim 7, further comprising:

converting the second GeO₂ layer on the common SiGe epitaxial layer to the plurality of top source/drain regions in the second device region to a second SiO₂ layer, and

removing a remaining amount of the second GeO₂ layer.

9. The method according to claim 8, wherein the converting step comprises heating the device in the presence of an inert gas such that the germanium in the second GeO₂ layer diffuses into the common SiGe epitaxial layer to the plurality of top source/drain regions to provide an increased amount of germanium, and an amount of silicon in the SiGe epitaxial layer diffuses into and converts the second GeO₂ layer to a second SiO₂ layer.

10. The method according to claim 8, further comprising:

forming a plurality of top source/drain regions extending from the exposed portion of the top surface of the first portion of the first plurality of fins; and

removing the second SiO₂ layer and the common SiGe epitaxial layer to the plurality of top source/drain regions in the second device region.

11. The method according to claim 10, wherein the top source/drain regions extending from the exposed portion of the top surface of the first portion of the first plurality of fins are in a triangle shaped configuration.

12. The method according to claim 1, further comprising forming a plurality of bottom source/drain regions on the substrate and around a portion of the first portion of the first plurality of fins in the first device region and around a lower portion of the second plurality of fins in the second device region.

13. The method according to claim 12, wherein the bottom source/drain region in the first device region comprises a boron doped silicon-germanium epitaxial material and the bottom source/drain region in the second device region comprises a phosphorus doped silicon epitaxial material.

14. The method according to claim 1, wherein the first and second device regions respectively comprise p-type and n-type transistor regions.

15. The method according to claim 1, wherein the plurality of metal gate layers comprises a gate dielectric layer in the first device region and the second device region.

16. A vertical transistor device, comprising:

a first plurality of Si fins disposed in a first device region on a substrate;

a second plurality of Si fins disposed in a second device region on the substrate;

a first metal gate layer disposed on the substrate and on a portion of sidewalls of the first plurality of fins in the first device region;

a second metal gate layer disposed on the substrate and on a portion of sidewalls of the second plurality of fins in the second device region;

a first spacer layer disposed on the first metal gate layer and on a remaining portion of the sidewalls of the first plurality of fins;

a second spacer layer disposed on the second metal gate layer and on another portion of the sidewalls of the second plurality of fins thereby exposing a remaining portion of the second plurality of fins above a top surface of the second spacer layer;

a dielectric layer disposed on and up to the top surface of the spacer layer;

a plurality of top source/drain regions extending from an exposed top surface of the first plurality of fins in the first device region, wherein the top source/drain regions in the first device region are in a triangle shaped configuration; and

a plurality of top source/drain regions extending from an exposed top surface of the second plurality of fins in the second device region, wherein the top source/drain regions in the second device region are in a diamond shaped configuration, and

wherein the first and second device regions respectively comprise p-type and n-type transistor regions.

17. The vertical transistor device according to claim 16, further comprising:

a plurality of bottom source/drain regions on the substrate and around lower portions of each of the first and second plurality of fins in the first and second device regions.

18. The vertical transistor device according to claim 17, wherein the bottom source/drain region in the first device region comprises a boron doped silicon-germanium epitaxial material and the bottom source/drain region in the second device region comprises a phosphorus doped silicon epitaxial material.

19. The vertical transistor device according to claim 16, further comprising a plurality of bottom source/drain regions on the substrate and around a lower portion of the first plurality of fins in the first device region and around a lower portion of the second plurality of fins in the second device region.

20. An integrated circuit, comprising:

a plurality of vertical transistor device, wherein at least one of the vertical transistor devices comprises;

a first plurality of Si fins disposed in a first device region on a substrate;

a second plurality of Si fins disposed in a second device region on the substrate;

a first metal gate layer disposed on the substrate and on a portion of sidewalls of the first plurality of fins in the first device region;

a second metal gate layer disposed on the substrate and on a portion of sidewalls of the second plurality of fins in the second device region;

a first spacer layer disposed on the first metal gate layer and on a remaining portion of the sidewalls of the first plurality of fins;

a second spacer layer disposed on the second metal gate layer and on another portion of the sidewalls of the second plurality of fins thereby exposing a remaining portion of the second plurality of fins above a top surface of the second spacer layer;

a dielectric layer disposed on and up to the top surface of the spacer layer;

a plurality of top source/drain regions extending from an exposed top surface of the first plurality of fins in the first device region, wherein the top source/drain regions in the first device region are in a triangle shaped configuration; and

a plurality of top source/drain regions extending from an exposed top surface of the second plurality of fins in the second device region, wherein the top source/drain regions in the second device region are in a diamond shaped configuration, and

wherein the first and second device regions respectively comprise p-type and n-type transistor regions.