METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

• US 20200135586A1
• Filed: 05/06/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, CHUN HSIUNG, PENG, CHENG-YI, LEE, CHING-HUA, WANN, CLEMENT HSINGJEN, LIN, YU-MING
• Granted Patent: US 11,133,222 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first transistor with a first conductive region and a second transistor with a second conductive region, wherein the first transistor and the second transistor have different conductive types. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate after the amorphization. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region after the formation of the pre-silicide layer.

Claims

1. A method for manufacturing a semiconductor structure, comprising:

receiving a substrate including a first transistor with a first conductive region and a second transistor with a second conductive region, wherein the first transistor and the second transistor have different conductive types;

performing a first laser anneal on the first conductive region;

performing a first amorphization on the first conductive region and the second conductive region;

forming a pre-silicide layer on the substrate;

performing a thermal anneal to the substrate to form a silicide layer; and

performing a second laser anneal on the first conductive region and the second conductive region after the formation of the pre-silicide layer.

2. The method of claim 1, wherein the first laser anneal and the second laser anneal are within micro-seconds respectively.

3. The method of claim 1, wherein the thermal anneal is a rapid thermal annealing, and a duration of the thermal anneal is in a range of 10-30 seconds.

4. The method of claim 1, further comprising:

performing a second amorphization, prior to the first laser anneal, on the first conductive region of the first transistor to define a vertical dopant profile in the first conductive region;

performing an implantation to the first conductive region.

5. The method of claim 4, further comprising:

forming a dielectric layer over the substrate after the performance of the implantation; and

performing a directional etching to remove a first portion of the dielectric layer and expose the first conductive region and the second conductive region.

6. The method of claim 5, wherein a second portion of the dielectric layer is remained on lateral sidewalls of a gate structure formed over the substrate.

7. The method of claim 1, wherein the thermal anneal is performed after the second laser anneal.

8. The method of claim 1, wherein the second laser anneal is performed after the thermal anneal.

9. A method for manufacturing a semiconductor structure, comprising:

receiving a substrate including a first conductive region and a second conductive region;

forming a first amorphous structure in the first conductive region;

introducing a substance into the first amorphous structure;

crystallizing the first amorphous structure;

forming a second amorphous structure and a third amorphous structure in the first conductive region and the second conductive regions respectively;

depositing a pre-silicide layer on the substrate;

forming a silicide layer from the pre-silicide layer; and

crystallizing the second amorphous structure and the third amorphous structure after the deposition of the pre-silicide layer.

10. The method of claim 9, wherein the substance includes boron.

11. The method of claim 9, wherein the silicide layer is formed in a designed phase transformation by a rapid thermal anneal.

12. The method of claim 11, wherein a temperature of the rapid thermal anneal is in a range from 500 to 650 degrees Celsius, and a duration of the rapid thermal anneal is in a range from 10 to 30 seconds.

13. The method of claim 9, wherein the crystallization of the first amorphous structure comprises:

performing a first laser anneal on the first conductive region.

14. The method of claim 13, wherein, wherein a duration of the first laser anneal is in a range from 200 to 400 microseconds, and a temperature of the first laser anneal is in a range from 800 to 950 degrees Celsius.

15. The method of claim 9, wherein the crystallization of the second amorphous structure and the third amorphous structure comprises:

performing a second laser anneal to the first conductive region and the second conductive region.

16. The method of claim 15, wherein a duration of the second laser anneal is in a range from 200 to 400 microseconds, and a temperature of the second laser anneal is in a range from 800 to 950 degrees Celsius.

17. The method of claim 9, wherein the formation of the first amorphous structure comprises:

performing an amorphization on the first conductive region to damage crystal lattices of the first conductive region, thereby forming the first amorphous structure in the first conductive region.

18. The method of claim 17, wherein the amorphization includes implantation with elements selected from:

germanium, silicon, argon, or any combination thereof.

19. A method for manufacturing a semiconductor structure, comprising:

receiving a substrate, including a first type transistor having a first epitaxial region and a second type transistor having a second epitaxial region;

doping the first epitaxial region, thereby forming a first lattice damaged structure in the first epitaxial region;

performing a first laser anneal to transform the first lattice damaged structure into a first polycrystalline structure;

performing a first amorphization on the first polycrystalline structure and the second epitaxial region to form a second lattice damaged structure from the first polycrystalline structure and a third lattice damaged structure in the second epitaxial region;

forming a pre-silicide layer covering the first epitaxial region and the second epitaxial region;

performing a thermal anneal; and

performing a second laser anneal to transform the second lattice damaged region into a second polycrystalline region in the first epitaxial structure and the third lattice damaged region into a second polycrystalline region in the second epitaxial structure.

20. The method of claim 19, wherein the doping of the first epitaxial region comprises:

performing a second amorphization on the first epitaxial region to form the first lattice damaged structure; and

performing an implantation to introduce ions into the first lattice damaged structure.