METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

• US 20200135587A1
• Filed: 05/30/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHENG, Chao-Ching, CHEN, I-Sheng, CHIANG, Hung-Li, CHEN, Tzu-Chiang, CHANG, Kai-Tai
• Granted Patent: US 11,335,604 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure, the upper fin structure including first semiconductor layers and second semiconductor layers alternately stacked;

partially etching the first semiconductor layers to reduce widths of the first semiconductor layers;

forming an oxide layer over the upper fin structure;

forming a sacrificial gate structure over the upper fin structure with the oxide layer;

forming a source/drain epitaxial layer over a source/drain region of the fin structure;

removing the sacrificial gate structure to form a gate space;

removing the oxide layer to expose the second semiconductor layers in the gate space; and

forming a gate structure around the second semiconductor layers in the gate space.

2. The method of claim 1, wherein the oxide layer is formed by thermal oxidation.

3. The method of claim 2, wherein after the thermal oxidation, an annealing operation is performed.

4. The method of claim 3, wherein the annealing operation is performed at 800°

C. to 1000°

C.

5. The method of claim 2, wherein the etched first semiconductor layers are fully oxidized by the thermal oxidation.

6. The method of claim 2, wherein the etched first semiconductor layers are partially oxidized by the thermal oxidation.

7. The method of claim 6, wherein after the oxide layer is removed in the gate space, the first semiconductor layers are removed in the gate space.

8. The method of claim 1, wherein, before the source/drain epitaxial layer is formed, the oxide layer in the source/drain region is removed.

9. The method of claim 8, wherein the source/drain epitaxial layer wraps around the second semiconductor layers in the source/drain region.

10. The method of claim 1, wherein part of the oxide layer remains between the source/drain epitaxial layer and the gate structure.

11. The method of claim 1, further comprising forming an isolation insulating layer around the lower fin structure after the first semiconductor layers are partially etched.

12. The method of claim 1, wherein:

the sacrificial gate structure includes a sacrificial gate electrode, and

the sacrificial gate electrode is in contact with the oxide layer.

13. The method of claim 1, wherein the first semiconductor layers are made of SiGe and the second semiconductor layers are made of Si.

14. A method of manufacturing a semiconductor device, comprising:

forming a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure, the upper fin structure including first semiconductor layers and second semiconductor layers alternately stacked;

partially etching the first semiconductor layers to reduce widths of the first semiconductor layers;

forming an oxide layer over the upper fin structure;

forming a sacrificial gate structure over the upper fin structure with the oxide layer;

forming a source/drain epitaxial layer over a source/drain region of the fin structure;

removing the sacrificial gate structure to form a gate space;

removing the oxide layer in the gate space to expose the second semiconductor layers in the gate space;

forming a third semiconductor layer on each of the exposed second semiconductor layers;

forming channel wires by mixing the third semiconductor layer and the second semiconductor layer; and

forming a gate structure around the channel wires in the gate space.

15. The method of claim 14, wherein:

the first semiconductor layers are made of SiGe,

the second semiconductor layers are made of Si, and

the third semiconductor layer is made of SiGe or Ge.

16. The method of claim 14, wherein the oxide layer is formed by thermal oxidation.

17. The method of claim 14, wherein the etched first semiconductors are fully oxidized by the thermal oxidation.

18. The method of claim 14, wherein part of the oxide layer remains between the source/drain epitaxial layer and the gate structure.

19. A semiconductor device, comprising:

a lower fin structure disposed over a substrate;

semiconductor wires disposed over the lower fin structure;

a gate structure disposed over channel regions of the semiconductor wires;

gate sidewall spacers disposed on opposite side faces of the gate structure; and

a source/drain epitaxial layer,

wherein an dielectric layer made of a different material than the gate sidewall spacers wraps around the semiconductor wires under the gate sidewall spacers.

20. The semiconductor device of claim 19, wherein the gate sidewall spacers are made of a silicon nitride based material and the dielectric layer is made of an oxide of at least one of Si and Ge.