Fin Field-Effect Transistor Device and Method

• US 20200135588A1
• Filed: 01/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Shao-Jyun, Pan, Sheng-Liang
• Granted Patent: US 10,872,826 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32105 Oxidation of silicon-containing layers
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first recess and in the second recess; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first dummy gate structure and a second dummy gate structure over a fin;

forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure;

removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively;

forming a gate dielectric layer in the first recess and the second recess;

forming a first work function layer over the gate dielectric layer in the first recess and in the second recess;

removing the first work function layer from the first recess;

converting a surface layer of the first work function layer in the second recess into an oxide; and

forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

2. The method of claim 1, wherein the second work function layer in the second recess over the oxide is thicker than the second work function layer in the first recess over the gate dielectric layer.

3. The method of claim 2, further comprising filling the first recess and the second recess with a conductive material to form a first metal gate and a second metal gate, respectively.

4. The method of claim 1, wherein removing the first work function layer from the first recess comprises:

forming a patterned mask layer in the second recess to cover the first work function layer in the second recess, wherein the first work function layer in the first recess is exposed by the patterned mask layer;

performing an etching process to remove the exposed first work function layer in the first recess; and

after performing the etching process, performing a plasma process to remove the patterned mask layer in the second recess.

5. The method of claim 4, wherein performing the etching process comprises performing a wet etch process using an etchant that is selective to a material of the first work function layer.

6. The method of claim 4, wherein the patterned mask layer comprises oxygen, and the plasma process generates oxygen species from the patterned mask layer, wherein converting the surface layer of the first work function layer comprises converting the surface layer of the first work function layer into the oxide using the oxygen species from the patterned mask layer.

7. The method of claim 6, wherein converting the surface layer of the first work function layer and performing the plasma process are performed in a same processing step.

8. The method of claim 1, wherein forming the first work function layer comprises forming a p-type work function layer.

9. The method of claim 8, wherein forming the second work function layer comprises forming an n-type work function layer.

10. The method of claim 9, wherein the second work function layer in the first recess has a first thickness different from a second thickness of the second work function layer in the second recess.

11. The method of claim 9, wherein the first work function layer is formed using titanium silicon nitride, the second work function layer is formed using aluminum-doped titanium carbide, and the oxide is silicon oxide.

12. A method of forming a semiconductor device, the method comprising:

forming a first dummy gate and a second dummy gate over a fin;

forming an interlayer dielectric layer (ILD) around the first dummy gate and the second dummy gate; and

replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively, wherein the replacing comprises;

removing the first dummy gate and the second dummy gate to form a first recess and a second recess in the ILD, respectively;

forming a gate dielectric layer in the first recess and in the second recess;

forming a first work function layer in the second recess over the gate dielectric layer, wherein the gate dielectric layer in the first recess is exposed by the first work function layer;

forming a second work function layer in the first recess and in the second recess using a same deposition process, wherein the second work function layer is formed to be thicker in the second recess than in the first recess; and

filling the first recess and the second recess with a conductive material.

13. The method of claim 12, wherein forming the first work function layer in the second recess comprises:

depositing the first work function layer in the first recess and in the second recess;

forming a patterned mask layer to cover the first work function layer in the second recess;

removing the first work function layer in the first recess; and

removing the patterned mask layer.

14. The method of claim 13, wherein the patterned mask layer comprises oxygen, wherein removing the patterned mask layer comprises performing a plasma process to remove the patterned mask layer, wherein the plasma process coverts a surface layer of the first work function layer into an oxide.

15. The method of claim 14, wherein gases used in the plasma process are free of oxygen.

16. The method of claim 14, wherein the plasma process is performed using gases comprising nitrogen, wherein the method further comprises changing a thickness of the second work function layer in the second recess by changing a flow rate of the nitrogen in the plasma process or by changing a duration of the plasma process.

17. A semiconductor device comprising:

a first metal gate structure over a fin, wherein the first metal gate structure comprises a gate dielectric layer over the fin, a first work function layer over and contacting the gate dielectric layer, an oxide over the first work function layer, a second work function layer over the oxide, and a fill metal over the second work function layer;

a second metal gate structure over the fin and adjacent to the first metal gate structure, wherein the second metal gate structure comprises the gate dielectric layer over the fin, the second work function layer over and contacting the gate dielectric layer, and the fill metal over the second work function layer, wherein the second work function layer of the first metal gate structure is thicker than the second work function layer of the second metal gate structure; and

a source/drain region over the fin and between the first metal gate structure and the second metal gate structure.

18. The semiconductor device of claim 17, wherein the first work function layer comprises titanium silicon nitride, and the second work function layer comprises aluminum-doped titanium carbide.

19. The semiconductor device of claim 18, wherein the second work function layer of the first metal gate structure has a first thickness, and the second work function layer of the second metal gate structure has a second thickness, the first thickness is larger than the second thickness by about 2 angstroms to about 3 angstroms.

20. The semiconductor device of claim 17, wherein the first metal gate structure and the second metal gate structure are in a same p-type device region or a same n-type device region.