METHOD OF METAL GATE FORMATION AND STRUCTURES FORMED BY THE SAME

• US 20200135589A1
• Filed: 04/01/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, YI-JING, CHENG, YA-YUN, LIN, HAU-YU, CHEN, I-SHENG, HSU, CHIA-MING, KO, CHIH-HSIN, WANN, CLEMENT HSINGJEN
• Granted Patent: US 10,804,163 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a first pair of source/drain regions in the substrate;

disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions;

depositing a dielectric layer in the first trench;

depositing a barrier layer over the dielectric layer;

removing the barrier layer from the first trench to expose the dielectric layer;

depositing a work function layer over the dielectric layer in the first trench; and

depositing a conductive layer over the work function layer in the first trench.

2. The method according to claim 1, further comprising:

forming a second pair of source/drain regions having the second dopant type in the substrate; and

forming a second trench in the interlayer dielectric layer between the second pair of source/drain regions,

wherein depositing a barrier layer over the dielectric layer comprises depositing the barrier layer in the second trench.

3. The method according to claim 2, wherein removing the barrier layer from the first trench comprises keeping the barrier layer intact in the second trench.

4. The method according to claim 1, wherein depositing a barrier layer over the dielectric layer comprises depositing the barrier layer on a sidewall of the dielectric layer.

5. The method according to claim 1, further comprising forming an adhesive layer in the first trench over the work function layer prior to depositing the conductive layer in the first trench.

6. The method according to claim 1, wherein depositing an interlayer dielectric layer having a first trench between the first pair of source/drain regions comprises:

forming a dummy gate structure over the substrate;

depositing the interlayer dielectric layer to surround the dummy gate structure; and

removing the dummy gate structure to form the first trench.

7. The method according to claim 6, further comprising forming a spacer on a sidewall of the dummy gate structure, wherein removing the dummy gate structure to form the first trench comprises leaving the spacer to define the first trench.

8. The method according to claim 1, further comprising:

depositing a second barrier layer prior to depositing the work function layer;

performing an annealing operation; and

partially removing the second barrier layer subsequent to the annealing operation.

9. The method according to claim 1, wherein the conductive layer comprises a top surface having a first width and a bottom surface having a second width greater than the first width.

10. The method according to claim 1, wherein the conductive layer comprises a top surface having a first width, and a ratio between the first width and a maximal width of the conductive layer is less than about 30%.

11. The method according to claim 1, wherein the conductive layer comprises a maximal width, at a height measured from a surface of the substrate, between about 10% and about 30% of a height of the dielectric layer.

12. A method of forming a semiconductor structure, comprising:

forming a first pair of source/drain regions and a second pair of source/drain regions in a substrate;

depositing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions and a second trench between the second pair of source/drain regions;

depositing a gate dielectric layer in the first trench and the second trench, respectively;

depositing a barrier stack over the gate dielectric layer in the first trench and the second trench;

depositing a work function layer in the first trench and the second trench;

reducing a thickness of the barrier stack from the first trench while keeping the barrier stack intact in the second trench; and

depositing a conductive layer in the first trench and the second trench over the work function layer.

13. The method according to claim 12, further comprising performing an annealing operation on the semiconductor structure prior to reducing a thickness of the barrier stack from the first trench.

14. The semiconductor structure according to claim 12, further comprising performing a cleaning operation on the substrate prior to reducing a thickness of the barrier stack from the first trench.

15. The semiconductor structure according to claim 12, wherein reducing a thickness of the barrier stack from the first trench comprises removing the barrier stack from the first trench to expose the gate dielectric layer.

16. The semiconductor structure according to claim 12, wherein the barrier stack comprises at least one of titanium nitride, titanium silicon nitride and tantalum nitride.

17. The semiconductor structure according to claim 12, wherein the reducing a thickness of the barrier stack from the first trench comprises performing a wet etching operation.

18. A semiconductor structure, comprising:

a substrate;

a first pair of source/drain regions and a second pair of source/drain regions in the substrate;

a first gate stack and a second gate stack over the substrate between the first pair and the second pair of source/drain regions, respectively, each gate stack comprising;

a gate dielectric layer over the substrate;

a work function layer surrounded by the gate dielectric layer; and

a conductive layer surrounded by the work function layer,

wherein the first gate stack further includes a barrier layer, that is absent from the second gate stack, between the gate dielectric layer and the work function layer.

19. The semiconductor structure according to claim 18, wherein the conductive layer of each of the gate stacks comprises a top surface having a first width, and a ratio between the first width and a maximal width of the conductive layer is less than about 30%.

20. The semiconductor structure according to claim 18, further comprising an adhesive layer between the conductive layer and the work function layer in each of the gate stacks.