AIR GAP FORMATION BETWEEN GATE SPACER AND EPITAXY STRUCTURE
First Claim
1. A method, comprising:
- forming a gate stack over a semiconductor substrate;
forming a first spacer layer on a sidewall of the gate stack;
forming a sacrificial spacer film over the first spacer layer, the sacrificial spacer film having an outer portion furthest from the first spacer layer and an inner portion closest to the first spacer layer;
forming an epitaxy structure on the semiconductor substrate;
performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure, wherein an etch rate of the outer portion of the sacrificial spacer film in the etching process is slower than an etch rate of the inner portion of the sacrificial spacer film in the etching process; and
forming a second spacer layer to seal the gap.
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Abstract
A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.
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Citations
20 Claims
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1. A method, comprising:
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forming a gate stack over a semiconductor substrate; forming a first spacer layer on a sidewall of the gate stack; forming a sacrificial spacer film over the first spacer layer, the sacrificial spacer film having an outer portion furthest from the first spacer layer and an inner portion closest to the first spacer layer; forming an epitaxy structure on the semiconductor substrate; performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure, wherein an etch rate of the outer portion of the sacrificial spacer film in the etching process is slower than an etch rate of the inner portion of the sacrificial spacer film in the etching process; and forming a second spacer layer to seal the gap. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method, comprising:
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forming a first spacer layer over a first gate stack in an n-type field-effect transistor (NFET) region and a second gate stack in a p-type field-effect transistor (PFET) region; forming a p-type epitaxy structure in the PFET region; after forming the p-type epitaxy structure, forming a first sacrificial spacer film over the first spacer layer; after forming the first sacrificial spacer film, forming an n-type epitaxy structure in the NFET region; performing a first etching process on the first sacrificial spacer film to form a first gap between the first spacer layer and the n-type epitaxy structure; and forming a second spacer layer to seal the first gap. - View Dependent Claims (13, 14, 15, 16)
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17. A semiconductor device, comprising:
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a gate stack over a substrate; an epitaxy structure raised above the substrate; a first spacer on a sidewall of the gate stack, the first spacer and the epitaxy structure defining an air gap therebetween; a second spacer sealing the air gap between the first spacer and the epitaxy structure; and a dielectric residue in the air gap and having an upper portion and a lower portion under the upper portion, the upper portion of the dielectric residue having higher etch resistance to phosphoric acid than that of the lower portion of the dielectric residue. - View Dependent Claims (18, 19, 20)
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Specification