AIR GAP FORMATION BETWEEN GATE SPACER AND EPITAXY STRUCTURE

• US 20200135590A1
• Filed: 05/14/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LAI, Bo-Yu, LEE, Kai-Hsuan, LEE, Wei-Yang, YANG, Feng-Cheng, CHEN, Yen-Ming
• Granted Patent: US 10,861,753 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.

Claims

1. A method, comprising:

forming a gate stack over a semiconductor substrate;

forming a first spacer layer on a sidewall of the gate stack;

forming a sacrificial spacer film over the first spacer layer, the sacrificial spacer film having an outer portion furthest from the first spacer layer and an inner portion closest to the first spacer layer;

forming an epitaxy structure on the semiconductor substrate;

performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure, wherein an etch rate of the outer portion of the sacrificial spacer film in the etching process is slower than an etch rate of the inner portion of the sacrificial spacer film in the etching process; and

forming a second spacer layer to seal the gap.

2. The method of claim 1, wherein forming the epitaxy structure comprises:

etching the sacrificial spacer film and the first spacer layer to expose a portion of the semiconductor substrate;

forming a recess in the exposed portion of the semiconductor substrate; and

growing the epitaxy structure from the recess in the semiconductor substrate at least until reaching the outer portion of the sacrificial spacer film.

3. The method of claim 1, further comprising:

forming a protective cap over the epitaxy structure prior to performing the etching process on the sacrificial spacer film, wherein the protective cap has a slower etch rate in the etching process than that of the epitaxy structure.

4. The method of claim 3, wherein forming the protective cap is performed such that the protective cap has a lower phosphorus atomic concentration than the epitaxy structure.

5. The method of claim 3, wherein the etching process is performed such that the protective cap is removed from the epitaxy structure.

6. The method of claim 1, wherein the first spacer layer has a slower etch rate in the etching process than that of the sacrificial spacer film.

7. The method of claim 1, wherein the outer portion of the sacrificial spacer film is formed at a higher temperature than that of forming the inner portion of the sacrificial spacer film.

8. The method of claim 1, wherein forming the sacrificial spacer film is performed at a temperature increasing as time passes.

9. The method of claim 1, wherein forming the sacrificial spacer film comprises:

forming a dielectric layer over the first spacer layer;

forming a dopant source layer over the dielectric layer; and

diffusing a dopant from the dopant source layer into the dielectric layer.

10. The method of claim 9, wherein diffusing the dopant from the dopant source layer into the dielectric layer is performed using an annealing process.

11. The method of claim 9, further comprising:

removing the dopant source layer prior to performing the etching process on the sacrificial spacer film.

12. A method, comprising:

forming a first spacer layer over a first gate stack in an n-type field-effect transistor (NFET) region and a second gate stack in a p-type field-effect transistor (PFET) region;

forming a p-type epitaxy structure in the PFET region;

after forming the p-type epitaxy structure, forming a first sacrificial spacer film over the first spacer layer;

after forming the first sacrificial spacer film, forming an n-type epitaxy structure in the NFET region;

performing a first etching process on the first sacrificial spacer film to form a first gap between the first spacer layer and the n-type epitaxy structure; and

forming a second spacer layer to seal the first gap.

13. The method of claim 12, further comprising:

forming a second sacrificial spacer film over the first spacer layer prior to forming the p-type epitaxy structure; and

after forming the p-type epitaxy structure, performing a second etching process to remove the second sacrificial spacer film from the NFET region.

14. The method of claim 13, wherein the first sacrificial spacer film is formed after performing the second etching process.

15. The method of claim 12, wherein the first etching process is performed to further form a second gap between the first spacer layer and the p-type epitaxy structure.

16. The method of claim 12, further comprising:

prior to forming the n-type epitaxy structure, removing a first portion of the first sacrificial spacer film from the NFET region, wherein a second portion of the first sacrificial spacer film remains covering the p-type epitaxy structure after removing the first portion of the first sacrificial spacer film.

17. A semiconductor device, comprising:

a gate stack over a substrate;

an epitaxy structure raised above the substrate;

a first spacer on a sidewall of the gate stack, the first spacer and the epitaxy structure defining an air gap therebetween;

a second spacer sealing the air gap between the first spacer and the epitaxy structure; and

a dielectric residue in the air gap and having an upper portion and a lower portion under the upper portion, the upper portion of the dielectric residue having higher etch resistance to phosphoric acid than that of the lower portion of the dielectric residue.

18. The semiconductor device of claim 17, wherein the upper portion of the dielectric residue has a higher silicon-to-nitrogen atomic ratio than that of the lower portion of the dielectric residue.

19. The semiconductor device of claim 17, wherein the upper portion of the dielectric residue has a higher density than that of the lower portion of the dielectric residue.

20. The semiconductor device of claim 17, wherein the upper portion of the dielectric residue has a higher impurity concentration than that of the lower portion of the dielectric residue.